| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <20241121172737.255-3-quic_rlaggysh@quicinc.com>
Date: Thu, 21 Nov 2024 17:27:37 +0000
From: Raviteja Laggyshetty <quic_rlaggysh@...cinc.com>
To: Georgi Djakov <djakov@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>
CC: Odelu Kukatla <quic_okukatla@...cinc.com>,
Mike Tipton
<quic_mdtipton@...cinc.com>,
<linux-arm-msm@...r.kernel.org>, <linux-pm@...r.kernel.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: [PATCH 2/2] interconnect: qcom: sdx75: Drop QP0 related interconnect and BCM nodes
QP0 resource on sdx75 is managed by clk-rpmh.
There are no interconnect clients voting for QP0, hence dropping the
redundant nodes from topolgy to avoid the risk of overriding the vote
placed on QP0 using clk-rpmh.
Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@...cinc.com>
---
drivers/interconnect/qcom/sdx75.c | 25 -------
drivers/interconnect/qcom/sdx75.h | 118 +++++++++++++++---------------
2 files changed, 58 insertions(+), 85 deletions(-)
diff --git a/drivers/interconnect/qcom/sdx75.c b/drivers/interconnect/qcom/sdx75.c
index 7ef1f17f3292..4afcdc5f25a7 100644
--- a/drivers/interconnect/qcom/sdx75.c
+++ b/drivers/interconnect/qcom/sdx75.c
@@ -16,15 +16,6 @@
#include "icc-rpmh.h"
#include "sdx75.h"
-static struct qcom_icc_node qpic_core_master = {
- .name = "qpic_core_master",
- .id = SDX75_MASTER_QPIC_CORE,
- .channels = 1,
- .buswidth = 4,
- .num_links = 1,
- .links = { SDX75_SLAVE_QPIC_CORE },
-};
-
static struct qcom_icc_node qup0_core_master = {
.name = "qup0_core_master",
.id = SDX75_MASTER_QUP_CORE_0,
@@ -375,14 +366,6 @@ static struct qcom_icc_node xm_usb3 = {
.links = { SDX75_SLAVE_A1NOC_CFG },
};
-static struct qcom_icc_node qpic_core_slave = {
- .name = "qpic_core_slave",
- .id = SDX75_SLAVE_QPIC_CORE,
- .channels = 1,
- .buswidth = 4,
- .num_links = 0,
-};
-
static struct qcom_icc_node qup0_core_slave = {
.name = "qup0_core_slave",
.id = SDX75_SLAVE_QUP_CORE_0,
@@ -831,12 +814,6 @@ static struct qcom_icc_bcm bcm_mc0 = {
.nodes = { &ebi },
};
-static struct qcom_icc_bcm bcm_qp0 = {
- .name = "QP0",
- .num_nodes = 1,
- .nodes = { &qpic_core_slave },
-};
-
static struct qcom_icc_bcm bcm_qup0 = {
.name = "QUP0",
.keepalive = true,
@@ -903,9 +880,7 @@ static struct qcom_icc_bcm * const clk_virt_bcms[] = {
};
static struct qcom_icc_node * const clk_virt_nodes[] = {
- [MASTER_QPIC_CORE] = &qpic_core_master,
[MASTER_QUP_CORE_0] = &qup0_core_master,
- [SLAVE_QPIC_CORE] = &qpic_core_slave,
[SLAVE_QUP_CORE_0] = &qup0_core_slave,
};
diff --git a/drivers/interconnect/qcom/sdx75.h b/drivers/interconnect/qcom/sdx75.h
index 24e887159920..3fd2bfcdce84 100644
--- a/drivers/interconnect/qcom/sdx75.h
+++ b/drivers/interconnect/qcom/sdx75.h
@@ -33,65 +33,63 @@
#define SDX75_MASTER_QDSS_ETR 24
#define SDX75_MASTER_QDSS_ETR_1 25
#define SDX75_MASTER_QPIC 26
-#define SDX75_MASTER_QPIC_CORE 27
-#define SDX75_MASTER_QUP_0 28
-#define SDX75_MASTER_QUP_CORE_0 29
-#define SDX75_MASTER_SDCC_1 30
-#define SDX75_MASTER_SDCC_4 31
-#define SDX75_MASTER_SNOC_CFG 32
-#define SDX75_MASTER_SNOC_SF_MEM_NOC 33
-#define SDX75_MASTER_SYS_TCU 34
-#define SDX75_MASTER_USB3_0 35
-#define SDX75_SLAVE_A1NOC_CFG 36
-#define SDX75_SLAVE_ANOC_PCIE_GEM_NOC 37
-#define SDX75_SLAVE_AUDIO 38
-#define SDX75_SLAVE_CLK_CTL 39
-#define SDX75_SLAVE_CRYPTO_0_CFG 40
-#define SDX75_SLAVE_CNOC_MSS 41
-#define SDX75_SLAVE_DDRSS_CFG 42
-#define SDX75_SLAVE_EBI1 43
-#define SDX75_SLAVE_ETH0_CFG 44
-#define SDX75_SLAVE_ETH1_CFG 45
-#define SDX75_SLAVE_GEM_NOC_CFG 46
-#define SDX75_SLAVE_GEM_NOC_CNOC 47
-#define SDX75_SLAVE_ICBDI_MVMSS_CFG 48
-#define SDX75_SLAVE_IMEM 49
-#define SDX75_SLAVE_IMEM_CFG 50
-#define SDX75_SLAVE_IPA_CFG 51
-#define SDX75_SLAVE_IPC_ROUTER_CFG 52
-#define SDX75_SLAVE_LAGG_CFG 53
-#define SDX75_SLAVE_LLCC 54
-#define SDX75_SLAVE_MCCC_MASTER 55
-#define SDX75_SLAVE_MEM_NOC_PCIE_SNOC 56
-#define SDX75_SLAVE_PCIE_0 57
-#define SDX75_SLAVE_PCIE_1 58
-#define SDX75_SLAVE_PCIE_2 59
-#define SDX75_SLAVE_PCIE_0_CFG 60
-#define SDX75_SLAVE_PCIE_1_CFG 61
-#define SDX75_SLAVE_PCIE_2_CFG 62
-#define SDX75_SLAVE_PCIE_ANOC_CFG 63
-#define SDX75_SLAVE_PCIE_RSC_CFG 64
-#define SDX75_SLAVE_PDM 65
-#define SDX75_SLAVE_PRNG 66
-#define SDX75_SLAVE_QDSS_CFG 67
-#define SDX75_SLAVE_QDSS_STM 68
-#define SDX75_SLAVE_QPIC 69
-#define SDX75_SLAVE_QPIC_CORE 70
-#define SDX75_SLAVE_QUP_0 71
-#define SDX75_SLAVE_QUP_CORE_0 72
-#define SDX75_SLAVE_SDCC_1 73
-#define SDX75_SLAVE_SDCC_4 74
-#define SDX75_SLAVE_SERVICE_GEM_NOC 75
-#define SDX75_SLAVE_SERVICE_PCIE_ANOC 76
-#define SDX75_SLAVE_SERVICE_SNOC 77
-#define SDX75_SLAVE_SNOC_CFG 78
-#define SDX75_SLAVE_SNOC_GEM_NOC_SF 79
-#define SDX75_SLAVE_SNOOP_BWMON 80
-#define SDX75_SLAVE_SPMI_VGI_COEX 81
-#define SDX75_SLAVE_TCSR 82
-#define SDX75_SLAVE_TCU 83
-#define SDX75_SLAVE_TLMM 84
-#define SDX75_SLAVE_USB3 85
-#define SDX75_SLAVE_USB3_PHY_CFG 86
+#define SDX75_MASTER_QUP_0 27
+#define SDX75_MASTER_QUP_CORE_0 28
+#define SDX75_MASTER_SDCC_1 29
+#define SDX75_MASTER_SDCC_4 30
+#define SDX75_MASTER_SNOC_CFG 31
+#define SDX75_MASTER_SNOC_SF_MEM_NOC 32
+#define SDX75_MASTER_SYS_TCU 33
+#define SDX75_MASTER_USB3_0 34
+#define SDX75_SLAVE_A1NOC_CFG 35
+#define SDX75_SLAVE_ANOC_PCIE_GEM_NOC 36
+#define SDX75_SLAVE_AUDIO 37
+#define SDX75_SLAVE_CLK_CTL 38
+#define SDX75_SLAVE_CRYPTO_0_CFG 39
+#define SDX75_SLAVE_CNOC_MSS 40
+#define SDX75_SLAVE_DDRSS_CFG 41
+#define SDX75_SLAVE_EBI1 42
+#define SDX75_SLAVE_ETH0_CFG 43
+#define SDX75_SLAVE_ETH1_CFG 44
+#define SDX75_SLAVE_GEM_NOC_CFG 45
+#define SDX75_SLAVE_GEM_NOC_CNOC 46
+#define SDX75_SLAVE_ICBDI_MVMSS_CFG 47
+#define SDX75_SLAVE_IMEM 48
+#define SDX75_SLAVE_IMEM_CFG 49
+#define SDX75_SLAVE_IPA_CFG 50
+#define SDX75_SLAVE_IPC_ROUTER_CFG 51
+#define SDX75_SLAVE_LAGG_CFG 52
+#define SDX75_SLAVE_LLCC 53
+#define SDX75_SLAVE_MCCC_MASTER 54
+#define SDX75_SLAVE_MEM_NOC_PCIE_SNOC 55
+#define SDX75_SLAVE_PCIE_0 56
+#define SDX75_SLAVE_PCIE_1 57
+#define SDX75_SLAVE_PCIE_2 58
+#define SDX75_SLAVE_PCIE_0_CFG 59
+#define SDX75_SLAVE_PCIE_1_CFG 60
+#define SDX75_SLAVE_PCIE_2_CFG 61
+#define SDX75_SLAVE_PCIE_ANOC_CFG 62
+#define SDX75_SLAVE_PCIE_RSC_CFG 63
+#define SDX75_SLAVE_PDM 64
+#define SDX75_SLAVE_PRNG 65
+#define SDX75_SLAVE_QDSS_CFG 66
+#define SDX75_SLAVE_QDSS_STM 67
+#define SDX75_SLAVE_QPIC 68
+#define SDX75_SLAVE_QUP_0 69
+#define SDX75_SLAVE_QUP_CORE_0 70
+#define SDX75_SLAVE_SDCC_1 71
+#define SDX75_SLAVE_SDCC_4 72
+#define SDX75_SLAVE_SERVICE_GEM_NOC 73
+#define SDX75_SLAVE_SERVICE_PCIE_ANOC 74
+#define SDX75_SLAVE_SERVICE_SNOC 75
+#define SDX75_SLAVE_SNOC_CFG 76
+#define SDX75_SLAVE_SNOC_GEM_NOC_SF 77
+#define SDX75_SLAVE_SNOOP_BWMON 78
+#define SDX75_SLAVE_SPMI_VGI_COEX 79
+#define SDX75_SLAVE_TCSR 80
+#define SDX75_SLAVE_TCU 81
+#define SDX75_SLAVE_TLMM 82
+#define SDX75_SLAVE_USB3 83
+#define SDX75_SLAVE_USB3_PHY_CFG 84
#endif
--
2.39.2
Powered by blists - more mailing lists