linux-kernel - [PATCH v2 0/6] pci: qcom: Add QCS615 PCIe support

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Message-Id: <20241122023314.1616353-1-quic_ziyuzhan@quicinc.com>
Date: Fri, 22 Nov 2024 10:33:08 +0800
From: Ziyue Zhang <quic_ziyuzhan@...cinc.com>
To: vkoul@...nel.org, kishon@...nel.org, robh+dt@...nel.org,
        manivannan.sadhasivam@...aro.org, bhelgaas@...gle.com, kw@...ux.com,
        lpieralisi@...nel.org, quic_qianyu@...cinc.com, conor+dt@...nel.org,
        neil.armstrong@...aro.org, andersson@...nel.org,
        konradybcio@...nel.org
Cc: quic_tsoni@...cinc.com, quic_shashim@...cinc.com,
        quic_kaushalk@...cinc.com, quic_tdas@...cinc.com,
        quic_tingweiz@...cinc.com, quic_aiquny@...cinc.com, kernel@...cinc.com,
        linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-phy@...ts.infradead.org,
        Ziyue Zhang <quic_ziyuzhan@...cinc.com>,
        Krishna chaitanya chundru <quic_krichai@...cinc.com>
Subject: [PATCH v2 0/6] pci: qcom: Add QCS615 PCIe support 

This series adds document, phy, configs support for PCIe in QCS615.
The series depend on the following devicetree and smmu.

Base DT:
https://lore.kernel.org/all/20241104-add_initial_support_for_qcs615-v5-0-9dde8d7b80b0@quicinc.com/

APPS SMMU:
https://lore.kernel.org/all/20241105032107.9552-1-quic_qqzhou@quicinc.com/

Signed-off-by: Krishna chaitanya chundru <quic_krichai@...cinc.com>
Signed-off-by: Ziyue Zhang <quic_ziyuzhan@...cinc.com>
---
Have following changes:
	- Add compatible and phy compatible for qcs615 platform.
	- Add support for GEN3 x1 PCIe PHY found on Qualcomm QCS615 platform.
	- Add a new Document the QCS615 PCIe Controller
	- Add the compatible for QCS615 PCIe controller.
	- Add configurations in devicetree for PCIe, including registers, clocks, interrupts and phy setting sequence.
	- Add configurations in devicetree for PCIe, platform related gpios, PMIC regulators, etc.

Changes in v2:
- Update commit message for qcs615 phy
- Update qcs615 phy, using lowercase hex
- Removed redundant function
- split the soc dtsi and the platform dts into two changes
- Link to v1: https://lore.kernel.org/all/20241118082619.177201-1-quic_ziyuzhan@quicinc.com/

Krishna chaitanya chundru (5):
  dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the QCS615 QMP
    PCIe PHY Gen3 x1
  phy: qcom: qmp: Add phy register and clk setting for QCS615 PCIe
  dt-bindings: PCI: qcom: Document the QCS615 PCIe Controller
  PCI: qcom: Add QCS615 PCIe support
  arm64: dts: qcom: qcs615: enable pcie for qcs615 board dts

Ziyue Zhang (1):
  arm64: dts: qcom: qcs615: enable pcie for qcs615 soc

 .../bindings/pci/qcom,pcie-qcs615.yaml        | 161 ++++++++++++++++++
 .../phy/qcom,sc8280xp-qmp-pcie-phy.yaml       |   2 +
 arch/arm64/boot/dts/qcom/qcs615-ride.dts      |  42 +++++
 arch/arm64/boot/dts/qcom/qcs615.dtsi          | 158 +++++++++++++++++
 drivers/pci/controller/dwc/pcie-qcom.c        |   1 +
 drivers/phy/qualcomm/phy-qcom-qmp-pcie.c      | 105 ++++++++++++
 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h    |   1 +
 7 files changed, 470 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie-qcs615.yaml


base-commit: ee5d1329f3de0b8cb77084715c1179627a9d599c
-- 
2.34.1