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Message-ID: <c9971277-bc93-4e53-b20a-a6aac6df9023@quicinc.com>
Date: Fri, 22 Nov 2024 14:07:08 +0800
From: Xin Liu <quic_liuxin@...cinc.com>
To: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
CC: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Manivannan Sadhasivam
<manivannan.sadhasivam@...aro.org>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>, Vinod Koul <vkoul@...nel.org>,
"Kishon Vijay Abraham I" <kishon@...nel.org>,
Alim Akhtar
<alim.akhtar@...sung.com>,
Avri Altman <avri.altman@....com>,
Bart Van Assche
<bvanassche@....org>,
"Andy Gross" <agross@...nel.org>, <linux-arm-msm@...r.kernel.org>,
<linux-phy@...ts.infradead.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <linux-scsi@...r.kernel.org>,
<quic_jiegan@...cinc.com>, <quic_aiquny@...cinc.com>,
<quic_tingweiz@...cinc.com>, <quic_sayalil@...cinc.com>
Subject: Re: [PATCH v2 2/3] arm64: dts: qcom: qcs615: add UFS node
在 2024/11/22 1:00, Dmitry Baryshkov 写道:
> On Tue, Nov 19, 2024 at 10:20:49AM +0800, Xin Liu wrote:
>> From: Sayali Lokhande <quic_sayalil@...cinc.com>
>>
>> Add the UFS Host Controller node and its PHY for QCS615 SoC.
>>
>> Signed-off-by: Sayali Lokhande <quic_sayalil@...cinc.com>
>> Co-developed-by: Xin Liu <quic_liuxin@...cinc.com>
>> Signed-off-by: Xin Liu <quic_liuxin@...cinc.com>
>> ---
>> arch/arm64/boot/dts/qcom/qcs615.dtsi | 112 +++++++++++++++++++++++++++
>> 1 file changed, 112 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>> index 590beb37f441..ceceafb2e71f 100644
>> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>> @@ -458,6 +458,118 @@ mmss_noc: interconnect@...0000 {
>> qcom,bcm-voters = <&apps_bcm_voter>;
>> };
>>
>> + ufs_mem_hc: ufshc@...4000 {
>> + compatible = "qcom,qcs615-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
>> + reg = <0x0 0x01d84000 0x0 0x3000>, <0x0 0x01d90000 0x0 0x8000>;
>
> Please consider splitting to have one entry per line (and reg-names
> too).
Thank you for your comments. I will fix it next version.
>
>> + reg-names = "std", "ice";
>> +
>> + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
>> +
>> + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
>> + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
>> + <&gcc GCC_UFS_PHY_AHB_CLK>,
>> + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
>> + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
>> + <&rpmhcc RPMH_CXO_CLK>,
>> + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
>> + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>;
>> + clock-names = "core_clk",
>> + "bus_aggr_clk",
>> + "iface_clk",
>> + "core_clk_unipro",
>> + "core_clk_ice",
>
> Wrong indentation
>
> Other than that LGTM.
>
Thank you for your comments. I will fix it next version.
>
>> + "ref_clk",
>> + "tx_lane0_sync_clk",
>> + "rx_lane0_sync_clk";
>> +
>> + resets = <&gcc GCC_UFS_PHY_BCR>;
>> + reset-names = "rst";
>> +
>> + operating-points-v2 = <&ufs_opp_table>;
>> + interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
>> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
>> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
>> + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>;
>> + interconnect-names = "ufs-ddr",
>> + "cpu-ufs";
>> +
>> + power-domains = <&gcc UFS_PHY_GDSC>;
>> + required-opps = <&rpmhpd_opp_nom>;
>> +
>> + iommus = <&apps_smmu 0x300 0x0>;
>> + dma-coherent;
>> +
>> + lanes-per-direction = <1>;
>> +
>> + phys = <&ufs_mem_phy>;
>> + phy-names = "ufsphy";
>> +
>> + #reset-cells = <1>;
>> +
>> + status = "disabled";
>> +
>> + ufs_opp_table: opp-table {
>> + compatible = "operating-points-v2";
>> +
>> + opp-50000000 {
>> + opp-hz = /bits/ 64 <50000000>,
>> + /bits/ 64 <0>,
>> + /bits/ 64 <0>,
>> + /bits/ 64 <37500000>,
>> + /bits/ 64 <75000000>,
>> + /bits/ 64 <0>,
>> + /bits/ 64 <0>,
>> + /bits/ 64 <0>;
>> + required-opps = <&rpmhpd_opp_low_svs>;
>> + };
>> +
>> + opp-100000000 {
>> + opp-hz = /bits/ 64 <100000000>,
>> + /bits/ 64 <0>,
>> + /bits/ 64 <0>,
>> + /bits/ 64 <75000000>,
>> + /bits/ 64 <150000000>,
>> + /bits/ 64 <0>,
>> + /bits/ 64 <0>,
>> + /bits/ 64 <0>;
>> + required-opps = <&rpmhpd_opp_svs>;
>> + };
>> +
>> + opp-200000000 {
>> + opp-hz = /bits/ 64 <200000000>,
>> + /bits/ 64 <0>,
>> + /bits/ 64 <0>,
>> + /bits/ 64 <150000000>,
>> + /bits/ 64 <300000000>,
>> + /bits/ 64 <0>,
>> + /bits/ 64 <0>,
>> + /bits/ 64 <0>;
>> + required-opps = <&rpmhpd_opp_nom>;
>> + };
>> + };
>> + };
>> +
>> + ufs_mem_phy: phy@...7000 {
>> + compatible = "qcom,qcs615-qmp-ufs-phy", "qcom,sm6115-qmp-ufs-phy";
>> + reg = <0x0 0x01d87000 0x0 0xe00>;
>> + clocks = <&rpmhcc RPMH_CXO_CLK>,
>> + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
>> + <&gcc GCC_UFS_MEM_CLKREF_CLK>;
>> + clock-names = "ref",
>> + "ref_aux",
>> + "qref";
>> +
>> + power-domains = <&gcc UFS_PHY_GDSC>;
>> +
>> + resets = <&ufs_mem_hc 0>;
>> + reset-names = "ufsphy";
>> +
>> + #clock-cells = <1>;
>> + #phy-cells = <0>;
>> +
>> + status = "disabled";
>> + };
>> +
>> tcsr_mutex: hwlock@...0000 {
>> compatible = "qcom,tcsr-mutex";
>> reg = <0x0 0x01f40000 0x0 0x20000>;
>> --
>> 2.34.1
>>
>>
>> --
>> linux-phy mailing list
>> linux-phy@...ts.infradead.org
>> https://lists.infradead.org/mailman/listinfo/linux-phy
>
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