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Message-ID: <20241122124505.1688436-5-quic_mmanikan@quicinc.com>
Date: Fri, 22 Nov 2024 18:15:05 +0530
From: Manikanta Mylavarapu <quic_mmanikan@...cinc.com>
To: <andersson@...nel.org>, <linus.walleij@...aro.org>, <robh@...nel.org>,
<krzk+dt@...nel.org>, <conor+dt@...nel.org>, <konradybcio@...nel.org>,
<linux-arm-msm@...r.kernel.org>, <linux-gpio@...r.kernel.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>
CC: <quic_srichara@...cinc.com>, <quic_varada@...cinc.com>
Subject: [PATCH 4/4] arm64: dts: qcom: ipq5424: configure spi0 node for rdp466
Enable the SPI0 node and configure the associated gpio pins.
Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@...cinc.com>
---
arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts | 45 +++++++++++++++++++++
1 file changed, 45 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
index d4d31026a026..6256216ca764 100644
--- a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
+++ b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
@@ -23,6 +23,36 @@ &sleep_clk {
};
&tlmm {
+ spi0_default_state: spi0-default-state {
+ clk-pins {
+ pins = "gpio6";
+ function = "spi0_clk";
+ drive-strength = <8>;
+ bias-pull-down;
+ };
+
+ cs-pins {
+ pins = "gpio7";
+ function = "spi0_cs";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ miso-pins {
+ pins = "gpio8";
+ function = "spi0_miso";
+ drive-strength = <8>;
+ bias-pull-down;
+ };
+
+ mosi-pins {
+ pins = "gpio9";
+ function = "spi0_mosi";
+ drive-strength = <8>;
+ bias-pull-down;
+ };
+ };
+
sdc_default_state: sdc-default-state {
clk-pins {
pins = "gpio5";
@@ -57,3 +87,18 @@ &xo_board {
clock-frequency = <24000000>;
};
+&qupv3 {
+ spi0: spi@...0000 {
+ pinctrl-0 = <&spi0_default_state>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ flash@0 {
+ compatible = "micron,n25q128a11", "jedec,spi-nor";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <50000000>;
+ };
+ };
+};
--
2.34.1
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