linux-kernel - Re: [PATCH v2 2/2] arm64: dts: qcom: qcs615-ride: Enable ethernet node

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Message-ID: <75fb42cc-1cc5-4dd3-924c-e6fda4061f03@quicinc.com>
Date: Wed, 27 Nov 2024 15:00:38 +0800
From: Yijie Yang <quic_yijiyang@...cinc.com>
To: Andrew Lunn <andrew@...n.ch>,
        Konrad Dybcio
	<konrad.dybcio@....qualcomm.com>
CC: Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio
	<konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski
	<krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>,
        Richard Cochran
	<richardcochran@...il.com>,
        <linux-arm-msm@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>, <netdev@...r.kernel.org>
Subject: Re: [PATCH v2 2/2] arm64: dts: qcom: qcs615-ride: Enable ethernet
 node



On 2024-11-27 14:17, Yijie Yang wrote:
> 
> 
> On 2024-11-22 21:19, Andrew Lunn wrote:
>>>>>>    +&ethernet {
>>>>>> +    status = "okay";
>>>>>> +
>>>>>> +    pinctrl-0 = <&ethernet_defaults>;
>>>>>> +    pinctrl-names = "default";
>>>>>> +
>>>>>> +    phy-handle = <&rgmii_phy>;
>>>>>> +    phy-mode = "rgmii";
>>>>>
>>>>> That is unusual. Does the board have extra long clock lines?
>>>>
>>>> Do you mean to imply that using RGMII mode is unusual? While the 
>>>> EMAC controller supports various modes, due to hardware design 
>>>> limitations, only RGMII mode can be effectively implemented.
>>>
>>> Is that a board-specific issue, or something that concerns the SoC 
>>> itself?
>>
>> Lots of developers gets this wrong.... Searching the mainline list for
>> patchs getting it wrong and the explanation i have given in the past
>> might help.
>>
>> The usual setting here is 'rgmmii-id', which means something needs to
>> insert a 2ns delay on the clock lines. This is not always true, a very
>> small number of boards use extra long clock likes on the PCB to add
>> the needed 2ns delay.
>>
>> Now, if 'rgmii' does work, it means something else is broken
>> somewhere. I will let you find out what.
> 
> The 'rgmii' does function correctly, but it does not necessarily mean 
> that a time delay is required at the board level. The EPHY can also 
> compensate for the time skew.

I was mistaken earlier; it is actually the EMAC that will introduce a 
time skew by shifting the phase of the clock in 'rgmii' mode.

> 
>>
>>>>>> +    max-speed = <1000>;
>>>>>
>>>>> Why do you have this property? It is normally used to slow the MAC
>>>>> down because of issues at higher speeds.
>>>>
>>>> According to the databoot, the EMAC in RGMII mode can support speeds 
>>>> of up to 1Gbps.
>>>
>>> I believe the question Andrew is asking is "how is that effectively
>>> different from the default setting (omitting the property)?"
>>
>> Correct. If there are no issues at higher speeds, you don't need
>> this. phylib will ask the PHY what it is capable of, and limit the
>> negotiated speeds to its capabilities. Occasionally you do see an
>> RGMII PHY connected to a MII MAC, because a RGMII PHY is cheaper...
>>
>>     Andrew
> 
> It does unnecessary, I will remove it.
> 

-- 
Best Regards,
Yijie