linux-kernel - Re: [PATCH v2 2/2] x86: KVM: Advertise AMD's speculation control features

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Message-ID: <0ad3de06-19b1-4be4-968c-ad6ba072097c@yandex-team.ru>
Date: Wed, 27 Nov 2024 14:26:23 +0300
From: Maksim Davydov <davydov-max@...dex-team.ru>
To: Jim Mattson <jmattson@...gle.com>
Cc: kvm@...r.kernel.org, linux-kernel@...r.kernel.org, x86@...nel.org,
 babu.moger@....com, seanjc@...gle.com, mingo@...hat.com, bp@...en8.de,
 tglx@...utronix.de, dave.hansen@...ux.intel.com, hpa@...or.com,
 pbonzini@...hat.com
Subject: Re: [PATCH v2 2/2] x86: KVM: Advertise AMD's speculation control
 features



On 11/26/24 20:11, Jim Mattson wrote:
> On Tue, Nov 26, 2024 at 1:45 AM Maksim Davydov
> <davydov-max@...dex-team.ru> wrote:
>>
>> It seems helpful to expose to userspace some speculation control features
>> from 0x80000008_EBX function:
>> * 16 bit. IBRS always on. Indicates whether processor prefers that
>>    IBRS is always on. It simplifies speculation managing.
>> * 18 bit. IBRS is preferred over software solution. Indicates that
>>    software mitigations can be replaced with more performant IBRS.
>> * 19 bit. IBRS provides Same Mode Protection. Indicates that when IBRS
>>    is set indirect branch predictions are not influenced by any prior
>>    indirect branches.
>> * 29 bit. BTC_NO. Indicates that processor isn't affected by branch type
>>    confusion. It's used during mitigations setting up.
>> * 30 bit. IBPB clears return address predictor. It's used during
>>    mitigations setting up.
>>
>> Signed-off-by: Maksim Davydov <davydov-max@...dex-team.ru>
>> ---
>>   arch/x86/include/asm/cpufeatures.h | 3 +++
>>   arch/x86/kvm/cpuid.c               | 5 +++--
>>   2 files changed, 6 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
>> index f6be4fd2ead0..ba371d364c58 100644
>> --- a/arch/x86/include/asm/cpufeatures.h
>> +++ b/arch/x86/include/asm/cpufeatures.h
>> @@ -340,7 +340,10 @@
>>   #define X86_FEATURE_AMD_IBPB           (13*32+12) /* Indirect Branch Prediction Barrier */
>>   #define X86_FEATURE_AMD_IBRS           (13*32+14) /* Indirect Branch Restricted Speculation */
>>   #define X86_FEATURE_AMD_STIBP          (13*32+15) /* Single Thread Indirect Branch Predictors */
>> +#define X86_FEATURE_AMD_IBRS_ALWAYS_ON (13*32+16) /* Indirect Branch Restricted Speculation always-on preferred */
>>   #define X86_FEATURE_AMD_STIBP_ALWAYS_ON        (13*32+17) /* Single Thread Indirect Branch Predictors always-on preferred */
>> +#define X86_FEATURE_AMD_IBRS_PREFERRED (13*32+18) /* Indirect Branch Restricted Speculation is preferred over SW solution */
>> +#define X86_FEATURE_AMD_IBRS_SMP       (13*32+19) /* Indirect Branch Restricted Speculation provides Same Mode Protection */
> 
> "SMP" is an unfortunate overloading of an acronym with another
> well-known meaning. Perhaps "SAME_MODE"?
> 

Thanks a lot for reviewing!
Yep, you are right. I've missed that "SMP" can confuse someone. So, 
"X86_FEATURE_AMD_IBRS_SAME_MODE" seems pretty good because the similar 
name is used in APM. I'll prepare the third version soon.


>>   #define X86_FEATURE_AMD_PPIN           (13*32+23) /* "amd_ppin" Protected Processor Inventory Number */
>>   #define X86_FEATURE_AMD_SSBD           (13*32+24) /* Speculative Store Bypass Disable */
>>   #define X86_FEATURE_VIRT_SSBD          (13*32+25) /* "virt_ssbd" Virtualized Speculative Store Bypass Disable */
>> diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
>> index 30ce1bcfc47f..5b2d52913b18 100644
>> --- a/arch/x86/kvm/cpuid.c
>> +++ b/arch/x86/kvm/cpuid.c
>> @@ -754,8 +754,9 @@ void kvm_set_cpu_caps(void)
>>          kvm_cpu_cap_mask(CPUID_8000_0008_EBX,
>>                  F(CLZERO) | F(XSAVEERPTR) |
>>                  F(WBNOINVD) | F(AMD_IBPB) | F(AMD_IBRS) | F(AMD_SSBD) | F(VIRT_SSBD) |
>> -               F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_STIBP_ALWAYS_ON) |
>> -               F(AMD_PSFD)
>> +               F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_IBRS_ALWAYS_ON) |
>> +               F(AMD_STIBP_ALWAYS_ON) | F(AMD_IBRS_PREFERRED) |
>> +               F(AMD_IBRS_SMP) | F(AMD_PSFD) | F(BTC_NO) | F(AMD_IBPB_RET)
>>          );
> 
> Reviewed-by: Jim Mattson <jmattson@...gle.com>

-- 
Best regards,
Maksim Davydov