[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20241203112015.GBZ07pb74AGR-TDWt7@fat_crate.local>
Date: Tue, 3 Dec 2024 12:20:15 +0100
From: Borislav Petkov <bp@...en8.de>
To: Pawan Gupta <pawan.kumar.gupta@...ux.intel.com>
Cc: Josh Poimboeuf <jpoimboe@...nel.org>, x86@...nel.org,
linux-kernel@...r.kernel.org, amit@...nel.org, kvm@...r.kernel.org,
amit.shah@....com, thomas.lendacky@....com, tglx@...utronix.de,
peterz@...radead.org, corbet@....net, mingo@...hat.com,
dave.hansen@...ux.intel.com, hpa@...or.com, seanjc@...gle.com,
pbonzini@...hat.com, daniel.sneddon@...ux.intel.com,
kai.huang@...el.com, sandipan.das@....com,
boris.ostrovsky@...cle.com, Babu.Moger@....com,
david.kaplan@....com, dwmw@...zon.co.uk, andrew.cooper3@...rix.com
Subject: Re: [PATCH v2 1/2] x86/bugs: Don't fill RSB on VMEXIT with
eIBRS+retpoline
On Mon, Dec 02, 2024 at 03:35:21PM -0800, Pawan Gupta wrote:
> It is in this doc:
>
> https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/indirect-branch-restricted-speculation.html
>
I hope those URLs remain more stable than past experience shows.
> "Processors with enhanced IBRS still support the usage model where IBRS is
> set only in the OS/VMM for OSes that enable SMEP. To do this, such
> processors will ensure that guest behavior cannot control the RSB after a
> VM exit once IBRS is set, even if IBRS was not set at the time of the VM
> exit."
ACK, thanks.
Now, can we pls add those excerpts to Documentation/ and point to them from
the code so that it is crystal clear why it is ok?
Thx.
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
Powered by blists - more mailing lists