linux-kernel - [PATCH] coresight-etm4x: add isb() before reading the TRCSTATR

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Message-ID: <20241204101320.3692167-1-quic_yuanfang@quicinc.com>
Date: Wed, 4 Dec 2024 18:13:20 +0800
From: yuanfang zhang <quic_yuanfang@...cinc.com>
To: <suzuki.poulose@....com>, <mike.leach@...aro.org>,
        <james.clark@...aro.org>, <alexander.shishkin@...ux.intel.com>
CC: <coresight@...ts.linaro.org>, <linux-arm-kernel@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>
Subject: [PATCH] coresight-etm4x: add isb() before reading the TRCSTATR

From: Yuanfang Zhang <quic_yuanfang@...cinc.com>

As recommended by section 4.3.7 ("Synchronization when using system
instructions to progrom the trace unit") of ARM IHI 0064H.b, the
self-hosted trace analyzer must perform a Context synchronization
event between writing to the TRCPRGCTLR and reading the TRCSTATR.

Signed-off-by: Yuanfang Zhang <quic_yuanfang@...cinc.com>
---
 drivers/hwtracing/coresight/coresight-etm4x-core.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index 66d44a404ad0..5da2c523c30a 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -906,6 +906,7 @@ static void etm4_disable_hw(void *info)
 	tsb_csync();
 	etm4x_relaxed_write32(csa, control, TRCPRGCTLR);
 
+	isb();
 	/* wait for TRCSTATR.PMSTABLE to go to '1' */
 	if (coresight_timeout(csa, TRCSTATR, TRCSTATR_PMSTABLE_BIT, 1))
 		dev_err(etm_dev,
-- 
2.34.1