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Message-ID: <7860c682-f6a8-4b97-86bc-c5e706a7bb34@arm.com>
Date: Wed, 4 Dec 2024 10:21:11 +0000
From: Suzuki K Poulose <suzuki.poulose@....com>
To: yuanfang zhang <quic_yuanfang@...cinc.com>, mike.leach@...aro.org,
james.clark@...aro.org, alexander.shishkin@...ux.intel.com
Cc: coresight@...ts.linaro.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH] coresight-etm4x: add isb() before reading the TRCSTATR
Hi
On 04/12/2024 10:13, yuanfang zhang wrote:
> From: Yuanfang Zhang <quic_yuanfang@...cinc.com>
>
> As recommended by section 4.3.7 ("Synchronization when using system
> instructions to progrom the trace unit") of ARM IHI 0064H.b, the
> self-hosted trace analyzer must perform a Context synchronization
> event between writing to the TRCPRGCTLR and reading the TRCSTATR.
>
Thanks for the patch. Please could you add the above in a comment
in the changes below ?
Also, add Fixes tag ? (It may go all the way back to initial support)
Otherwise looks sensible to me.
Suzuki
> Signed-off-by: Yuanfang Zhang <quic_yuanfang@...cinc.com>
> ---
> drivers/hwtracing/coresight/coresight-etm4x-core.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> index 66d44a404ad0..5da2c523c30a 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> @@ -906,6 +906,7 @@ static void etm4_disable_hw(void *info)
> tsb_csync();
> etm4x_relaxed_write32(csa, control, TRCPRGCTLR);
>
> + isb();
> /* wait for TRCSTATR.PMSTABLE to go to '1' */
> if (coresight_timeout(csa, TRCSTATR, TRCSTATR_PMSTABLE_BIT, 1))
> dev_err(etm_dev,
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