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Message-ID: <d65354a0-c4b8-4379-b824-f4541718a3c2@tuxon.dev>
Date: Mon, 9 Dec 2024 13:14:09 +0200
From: Claudiu Beznea <claudiu.beznea@...on.dev>
To: Geert Uytterhoeven <geert@...ux-m68k.org>
Cc: mturquette@...libre.com, sboyd@...nel.org, robh@...nel.org,
krzk+dt@...nel.org, conor+dt@...nel.org, biju.das.jz@...renesas.com,
prabhakar.mahadev-lad.rj@...renesas.com, lgirdwood@...il.com,
broonie@...nel.org, magnus.damm@...il.com, linus.walleij@...aro.org,
perex@...ex.cz, tiwai@...e.com, p.zabel@...gutronix.de,
linux-renesas-soc@...r.kernel.org, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-sound@...r.kernel.org, linux-gpio@...r.kernel.org,
Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
Subject: Re: [PATCH v3 02/25] clk: versaclock3: Prepare for the addition of
5L35023 device
Hi, Geert,
On 09.12.2024 12:57, Geert Uytterhoeven wrote:
> Hi Claudiu,
>
> On Wed, Nov 13, 2024 at 2:35 PM Claudiu <claudiu.beznea@...on.dev> wrote:
>> From: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
>>
>> The 5P35023 and 5L35035 Versa 3 clock generator variants are different but
>> the versaclock3 driver could be used with small adjustments. The features
>> that are implemented in driver and differs b/w variants are the PLL2 Fvco
>> and clock sel bit for SE2 clock. Adjust the driver to prepare for the
>> addition of 5L35023 device.
>>
>> Reviewed-by: Biju Das <biju.das.jz@...renesas.com>
>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
>
> Thanks for your patch!
>
>> --- a/drivers/clk/clk-versaclock3.c
>> +++ b/drivers/clk/clk-versaclock3.c
>> @@ -166,12 +167,17 @@ struct vc3_div_data {
>> struct vc3_hw_data {
>> struct clk_hw hw;
>> struct regmap *regmap;
>> - const void *data;
>> + void *data;
>>
>> u32 div_int;
>> u32 div_frc;
>> };
>
>> @@ -698,8 +706,6 @@ static struct vc3_hw_data clk_pll[] = {
>> .num = VC3_PLL2,
>> .int_div_msb_offs = VC3_PLL2_FB_INT_DIV_MSB,
>> .int_div_lsb_offs = VC3_PLL2_FB_INT_DIV_LSB,
>> - .vco_min = VC3_PLL2_VCO_MIN,
>> - .vco_max = VC3_PLL2_VCO_MAX
>> },
>> .hw.init = &(struct clk_init_data) {
>> .name = "pll2",
>
>> @@ -1029,9 +1037,16 @@ static int vc3_probe(struct i2c_client *client)
>> clk_pfd[i].hw.init->name);
>> }
>>
>> + data = i2c_get_match_data(client);
>> +
>> /* Register pll's */
>> for (i = 0; i < ARRAY_SIZE(clk_pll); i++) {
>> clk_pll[i].regmap = regmap;
>> + if (i == VC3_PLL2) {
>> + struct vc3_pll_data *pll_data = clk_pll[i].data;
>> +
>> + pll_data->vco = data->pll2_vco;
>
> You cannot modify the global clk_pll[] data, as it is shared when
> there are multiple instances.
By "multiple instances" do you mean, multiple versa3 devices using this
driver? Do you know if we have such a board integrated, ATM?
Thank you,
Claudiu
> Oops, the driver already did this before, as the .regmap, .div_int,
> and .div_frc fields are modified during operation.
>
>> + }
>> ret = devm_clk_hw_register(dev, &clk_pll[i].hw);
>> if (ret)
>> return dev_err_probe(dev, ret, "%s failed\n",
>> @@ -1059,6 +1074,11 @@ static int vc3_probe(struct i2c_client *client)
>> /* Register clk muxes */
>> for (i = 0; i < ARRAY_SIZE(clk_mux); i++) {
>> clk_mux[i].regmap = regmap;
>> + if (i == VC3_SE2_MUX) {
>> + struct vc3_clk_data *clk_data = clk_mux[i].data;
>> +
>> + clk_data->bitmsk = data->se2_clk_sel_msk;
>> + }
>
> Likewise.
>
>> ret = devm_clk_hw_register(dev, &clk_mux[i].hw);
>> if (ret)
>> return dev_err_probe(dev, ret, "%s failed\n",
>
> Gr{oetje,eeting}s,
>
> Geert
>
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