linux-kernel - Re: [PATCH v6 0/5] Add CMN PLL clock controller driver for IPQ9574

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Message-ID: <25619909-90c2-40a8-9e49-83ab26b6cf79@quicinc.com>
Date: Mon, 9 Dec 2024 20:10:58 +0800
From: Jie Luo <quic_luoj@...cinc.com>
To: Bjorn Andersson <andersson@...nel.org>,
        Michael Turquette
	<mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>, Rob Herring
	<robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley
	<conor+dt@...nel.org>,
        Catalin Marinas <catalin.marinas@....com>,
        Will Deacon
	<will@...nel.org>, Konrad Dybcio <konradybcio@...nel.org>,
        <dmitry.baryshkov@...aro.org>
CC: <linux-arm-msm@...r.kernel.org>, <linux-clk@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>, <quic_kkumarcs@...cinc.com>,
        <quic_suruchia@...cinc.com>, <quic_pavir@...cinc.com>,
        <quic_linchen@...cinc.com>, <quic_leiwei@...cinc.com>,
        <bartosz.golaszewski@...aro.org>, <srinivas.kandagatla@...aro.org>,
        "Krzysztof Kozlowski" <krzysztof.kozlowski@...aro.org>
Subject: Re: [PATCH v6 0/5] Add CMN PLL clock controller driver for IPQ9574



On 11/6/2024 6:52 PM, Luo Jie wrote:
> The CMN PLL clock controller in Qualcomm IPQ chipsets provides
> the clocks to the networking hardware blocks that are internal
> or external to the SoC, and to the GCC. This driver configures
> the CMN PLL clock controller to enable the output clocks. The
> networking blocks include the internal blocks such as PPE
> (Packet Process Engine) and PCS blocks, and external hardware
> such as Ethernet PHY or switch. The CMN PLL block also outputs
> fixed rate clocks to GCC, such as 24 MHZ as XO clock and 32 KHZ
> as sleep clock supplied to GCC.
> 
> The controller expects the input reference clock from the internal
> Wi-Fi block acting as the clock source. The output clocks supplied
> by the controller are fixed rate clocks.
> 
> The CMN PLL hardware block does not include any other function
> other than enabling the clocks to the networking hardware blocks
> and GCC.
> 
> The driver is being enabled to support IPQ9574 SoC initially, and
> will be extended for other SoCs.
> 
> Signed-off-by: Luo Jie <quic_luoj@...cinc.com>
> ---
> Changes in v6:
> - Rename the reference clock of CMN PLL to ref_48mhz_clk.
> - Add the patch to update xo_board_clk to use fixed factor clock.
> - Link to v5: https://lore.kernel.org/r/20241028-qcom_ipq_cmnpll-v5-0-339994b0388d@quicinc.com
> 
> Changes in v5:
> - Move the hardware configurations into set_rate() from determine_rate().
> - Remove the dependency on IPQ_GCC_9574.
> - Correct the header files included.
> - Update reference clock of CMN PLL to use fixed factor clock.
> - Link to v4: https://lore.kernel.org/r/20241015-qcom_ipq_cmnpll-v4-0-27817fbe3505@quicinc.com
> 
> Changes in v4:
> - Rename driver file to ipq-cmn-pll.c
> - Register CMN PLL as a 12 GHZ clock.
> - Configure CMN PLL input ref clock using clk_ops::determine_rate().
>    Add the additional output clocks to GCC and PCS.
> - Update the same information in dtbindings.
> - Use PM clock APIs for input clock enablement.
> - Link to v3: https://lore.kernel.org/r/20240827-qcom_ipq_cmnpll-v3-0-8e009cece8b2@quicinc.com
> 
> Changes in v3:
> - Update description of dt-binding to explain scope of 'CMN' in CMN PLL.
> - Collect Reviewed-by tags for dtbindings and defconfig patches.
> - Enable PLL_LOCKED check for the stability of output clocks.
> - Link to v2: https://lore.kernel.org/r/20240820-qcom_ipq_cmnpll-v2-0-b000dd335280@quicinc.com
> 
> Changes in v2:
> - Rename the dt-binding file with the compatible.
> - Remove property 'clock-output-names' from dt-bindings and define
>    names in the driver. Add qcom,ipq-cmn-pll.h to export the output
>    clock specifier.
> - Alphanumeric ordering of 'cmn_pll_ref_clk' node in DTS.
> - Fix allmodconfig error reported by test robot.
> - Replace usage of "common" to "CMN" to match the name with the
>    hardware specification.
> - Clarify in commit message on scope of CMN PLL function.
> - Link to v1: https://lore.kernel.org/r/20240808-qcom_ipq_cmnpll-v1-0-b0631dcbf785@quicinc.com
> 
> ---
> Luo Jie (5):
>        dt-bindings: clock: qcom: Add CMN PLL clock controller for IPQ SoC
>        clk: qcom: Add CMN PLL clock controller driver for IPQ SoC
>        arm64: defconfig: Enable Qualcomm IPQ CMN PLL clock controller
>        arm64: dts: qcom: Add CMN PLL node for IPQ9574 SoC
>        arm64: dts: qcom: Update IPQ9574 xo_board_clk to use fixed factor clock
> 
>   .../bindings/clock/qcom,ipq9574-cmn-pll.yaml       |  85 ++++
>   arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi   |  23 +-
>   arch/arm64/boot/dts/qcom/ipq9574.dtsi              |  27 +-
>   arch/arm64/configs/defconfig                       |   1 +
>   drivers/clk/qcom/Kconfig                           |   9 +
>   drivers/clk/qcom/Makefile                          |   1 +
>   drivers/clk/qcom/ipq-cmn-pll.c                     | 436 +++++++++++++++++++++
>   include/dt-bindings/clock/qcom,ipq-cmn-pll.h       |  22 ++
>   8 files changed, 601 insertions(+), 3 deletions(-)
> ---
> base-commit: d61a00525464bfc5fe92c6ad713350988e492b88
> change-id: 20241014-qcom_ipq_cmnpll-bde0638f4116
> 
> Best regards,

Hello Bjorn, Stephen, Dmitry,

Gentle reminder, to re-review the updated patch series V6 at your
convenience to let me know if this patch series is fine to be merged.
Thanks in advance.