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Message-ID: <Z1h2BDwcvbyroNx2@lizhi-Precision-Tower-5810>
Date: Tue, 10 Dec 2024 12:10:28 -0500
From: Frank Li <Frank.li@....com>
To: Krzysztof Kozlowski <krzk@...nel.org>
Cc: Lorenzo Pieralisi <lpieralisi@...nel.org>,
Krzysztof Wilczyński <kw@...ux.com>,
Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>,
Rob Herring <robh@...nel.org>, Bjorn Helgaas <bhelgaas@...gle.com>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Karthikeyan Mitran <m.karthikeyan@...iveil.co.in>,
Hou Zhiqiang <Zhiqiang.Hou@....com>, Frank <Li@....com>,
"open list:PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS" <linux-pci@...r.kernel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" <devicetree@...r.kernel.org>,
open list <linux-kernel@...r.kernel.org>, imx@...ts.linux.dev
Subject: Re: [PATCH v2 1/1] dt-bindings: PCI: mobiveil: convert
mobiveil-pcie.txt to yaml format
On Tue, Dec 10, 2024 at 09:52:47AM +0100, Krzysztof Kozlowski wrote:
> On Fri, Dec 06, 2024 at 05:25:27PM -0500, Frank Li wrote:
> > Convert device tree binding doc mobiveil-pcie.txt to yaml format. Merge
> > layerscape-pcie-gen4.txt into this file.
> >
> > Additional change:
> > - interrupt-names: "aer", "pme", "intr", which align order in examples.
> > - reg-names: csr_axi_slave, config_axi_slave, which align existed dts file.
>
> mobiveil-pcie.txt binding suggested reversed orders of above, so please
> mention that you unify the order to match layerscape-pcie-gen4 and
> existing Layerscape DTS users.
>
>
> ...
>
>
> > +++ b/Documentation/devicetree/bindings/pci/mbvl,gpex40-pcie.yaml
> > @@ -0,0 +1,167 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/pci/mbvl,gpex40-pcie.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Mobiveil AXI PCIe Root Port Bridge
> > +
> > +maintainers:
> > + - Frank Li <Frank Li@....com>
> > +
> > +description:
> > + Mobiveil's GPEX 4.0 is a PCIe Gen4 root port bridge IP. This configurable IP
> > + has up to 8 outbound and inbound windows for the address translation.
> > +
> > + NXP Layerscape PCIe Gen4 controller (Deprecated) base on Mobiveil's GPEX 4.0.
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - mbvl,gpex40-pcie
> > + - fsl,lx2160a-pcie
>
> Please reverse them to keep alphabetical order.
>
> > +
> > + reg:
> > + items:
> > + - description: PCIe controller registers
> > + - description: Bridge config registers
> > + - description: GPIO registers to control slot power
> > + - description: MSI registers
> > + minItems: 2
> > +
> > + reg-names:
> > + items:
> > + - const: csr_axi_slave
> > + - const: config_axi_slave
> > + - const: gpio_slave
> > + - const: apb_csr
> > + minItems: 2
> > +
> > + apio-wins:
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + description: |
> > + numbers of requested apio outbound windows
> > + 1. Config window
> > + 2. Memory window
> > + default: 2
> > + maximum: 256
> > +
> > + ppio-wins:
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + description: number of requested ppio inbound windows
> > + default: 1
> > + maximum: 256
> > +
> > + interrupt-controller: true
> > +
> > + "#interrupt-cells":
> > + const: 1
> > +
> > + interrupts:
> > + minItems: 1
> > + maxItems: 3
> > +
> > + interrupt-names:
> > + minItems: 1
> > + maxItems: 3
> > +
> > + dma-coherent: true
> > +
> > + msi-parent: true
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - reg-names
> > +
> > +allOf:
> > + - $ref: /schemas/pci/pci-host-bridge.yaml#
> > + - if:
> > + properties:
> > + compatible:
> > + enum:
> > + - fsl,lx2160a-pcie
> > + then:
> > + properties:
> > + reg:
> > + maxItems: 2
> > +
> > + reg-names:
> > + maxItems: 2
> > +
>
> interrupts:
> minItems: 3
>
> > + interrupt-names:
> > + items:
> > + - const: aer
> > + - const: pme
> > + - const: intr
> > + else:
> > + properties:
> > + dma-coherent: false
> > + msi-parent: false
>
> reg? interrupts? interrupt-names?
mbvl,gpex40-pcie text file descript reg as
Mandatory:
"config_axi_slave": PCIe controller registers
"csr_axi_slave" : Bridge config registers
Optional:
"gpio_slave" : GPIO registers to control slot power
"apb_csr" : MSI registers
reg have set minItems 2 and maxItems 4 at top. So needn't set it again.
I will add interrupts and interrupt-names.
Frank
>
>
>
> > +
> > +unevaluatedProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > + pcie@...00000 {
> > + compatible = "mbvl,gpex40-pcie";
> > + reg = <0xb0000000 0x00010000>,
> > + <0xa0000000 0x00001000>,
> > + <0xff000000 0x00200000>,
> > + <0xb0010000 0x00001000>;
> > + reg-names = "csr_axi_slave",
> > + "config_axi_slave",
> > + "gpio_slave",
> > + "apb_csr";
> > + #address-cells = <3>;
> > + #size-cells = <2>;
> > + device_type = "pci";
> > + apio-wins = <2>;
> > + ppio-wins = <1>;
> > + bus-range = <0x00000000 0x000000ff>;
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > + interrupt-parent = <&gic>;
> > + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-map-mask = <0 0 0 7>;
> > + interrupt-map = <0 0 0 0 &pci_express 0>,
> > + <0 0 0 1 &pci_express 1>,
> > + <0 0 0 2 &pci_express 2>,
> > + <0 0 0 3 &pci_express 3>;
> > + ranges = <0x83000000 0 0x00000000 0xa8000000 0 0x8000000>;
>
> Please keep ranges after reg-names
>
> > + };
> > +
> > + - |
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > + soc {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + pcie@...0000 {
> > + compatible = "fsl,lx2160a-pcie";
> > + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
> > + 0x80 0x00000000 0x0 0x00001000>; /* configuration space */
> > + reg-names = "csr_axi_slave", "config_axi_slave";
> > + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
> > + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
> > + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
> > + interrupt-names = "aer", "pme", "intr";
> > + #address-cells = <3>;
> > + #size-cells = <2>;
> > + device_type = "pci";
> > + apio-wins = <8>;
> > + ppio-wins = <8>;
> > + dma-coherent;
> > + bus-range = <0x0 0xff>;
> > + msi-parent = <&its>;
> > + ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>;
>
> Ditto here
>
> > + #interrupt-cells = <1>;
> > + interrupt-map-mask = <0 0 0 7>;
> > + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
> > + <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
> > + <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
> > + <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
> > + };
>
> Best regards,
> Krzysztof
>
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