linux-kernel - Re: [PATCH v1 0/7] Add support to load QUP SE firmware from

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Message-ID: <95a64663-2e48-400d-b4e9-a99e18e62825@quicinc.com>
Date: Tue, 10 Dec 2024 10:52:37 +0530
From: Viken Dadhaniya <quic_vdadhani@...cinc.com>
To: <neil.armstrong@...aro.org>,
        Konrad Dybcio
	<konrad.dybcio@....qualcomm.com>,
        <andi.shyti@...nel.org>, <robh@...nel.org>, <krzk+dt@...nel.org>,
        <conor+dt@...nel.org>, <gregkh@...uxfoundation.org>,
        <jirislaby@...nel.org>, <broonie@...nel.or>, <andersson@...nel.org>,
        <konradybcio@...nel.org>, <johan+linaro@...nel.org>,
        <dianders@...omium.org>, <agross@...nel.org>,
        <linux-arm-msm@...r.kernel.org>, <linux-i2c@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <linux-serial@...r.kernel.org>, <linux-spi@...r.kernel.org>
CC: Mukesh Kumar Savaliya <quic_msavaliy@...cinc.com>,
        <quic_anupkulk@...cinc.com>
Subject: Re: [PATCH v1 0/7] Add support to load QUP SE firmware from



On 12/9/2024 8:15 PM, neil.armstrong@...aro.org wrote:
> On 05/12/2024 16:59, Konrad Dybcio wrote:
>> On 4.12.2024 4:03 PM, Viken Dadhaniya wrote:
>>> In Qualcomm SoCs, firmware loading for Serial Engines (SE) in the QUP
>>> hardware has traditionally been managed by TrustZone (TZ). This setup
>>> handled Serial Engines(SE) assignments and access control permissions,
>>> ensuring a high level of security but limiting flexibility and
>>> accessibility.
>>> This limitation poses a significant challenge for developers who need 
>>> more
>>> flexibility to enable any protocol on any of the SEs within the QUP
>>> hardware.
>>> To address this, we are introducing a change that opens the firmware
>>> loading mechanism to the Linux environment. This enhancement increases
>>> flexibility and allows for more streamlined and efficient management. We
>>> can now handle SE assignments and access control permissions directly
>>> within Linux, eliminating the dependency on TZ.
>>> We propose an alternative method for firmware loading and SE
>>> ownership/transfer mode configuration based on device tree 
>>> configuration.
>>> This method does not rely on other execution environments, making it
>>> accessible to all developers.
>>> For SEs used prior to the kernel, their firmware will be loaded by the
>>> respective image drivers (e.g., Debug UART, Secure or trusted SE).
>>> Additionally, the GSI firmware, which is common to all SEs per QUPV3 
>>> core,
>>> will not be loaded by Linux driver but TZ only. At the kernel level, 
>>> only
>>> the SE protocol driver should load the respective protocol firmware.
>>
>> I think this is a great opportunity to rethink the SE node in general.
>>
>> Currently, for each supported protocol, we create a new node that
>> differs in (possibly) interconnects and pinctrl states. These are really
>> defined per-SE however and we can programmatically determine which ones
>> are relevant.
>>
>> With the growing number of protocols supported, we would have to add
>> 20+ nodes in some cases for each one of them. I think a good one would
>> look like:
>>
>> geni_se10: serial-engine@...def {
>>     compatible = "qcom,geni-se";
>>
>>     reg
>>     clocks
>>     power-domains
>>     interconnects
>>     ...
>>
>>     status
>>
>>     geni_se10_i2c: i2c {
>>         // i2c-controller.yaml
>>     };
>>
>>     geni_se10_spi: spi {
>>         // spi-controller.yaml
>>     };
>>
>>     ...
>> }
>>
>> Or maybe even get rid of the subnodes and restrict that to a single
>> se-protocol = <SE_PROTOCOL_xyz> property, if the bindings folks agree.
>>
>> We could extend the DMA APIs to dynamically determine the protocol
>> ID and get rid of hardcoding it.
>>
>> And then we could spawn an instance of the spi, i2c, etc. driver from
>> the GENI SE driver.
> 
> How/where would you add the peripheral subnodes ? A Serial Engine can 
> only be a
> single type on a board, but I agree we could have a "generic" serial 
> engine node
> that would be differenciated in the board DT with the protocol, and use 
> the bindings
> yaml checked to properly check the subnodes/properties depending on the 
> protocol
> property.
> 
> But we would still need all the serial nodes in the SoC DT.
> 
> This may make the software support harder, meaning we would either need to
> have the same compatible probed in sequence from the i2c/spi/uart driver 
> until
> one matches the protocol, or have the qup driver spawn an auxiliary device.
> 
> Honestly, not sure it would be much simpler...
> 

Agree Neil, it has it's own challenges in terms actual code changes per 
driver and common driver redesign when we move the SE nodes and make it 
common. We may come up with some solution to make one SE DTSI node for 
all protocols having different (pinctrl configuration, DMA 
configuration) but it's also going to add some level of code 
complexities and yaml changes.
Can we exclude this design change for this firmware loading and later 
align to this new design change ?

> Neil
> 
>>
>> Konrad
>>
>