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Message-ID: <761ef6ecfe8298f945e6627aff29f864fcf7b9c0.camel@mediatek.com>
Date: Wed, 11 Dec 2024 03:46:26 +0000
From: CK Hu (胡俊光) <ck.hu@...iatek.com>
To: "chunkuang.hu@...nel.org" <chunkuang.hu@...nel.org>, "AngeloGioacchino Del
Regno" <angelogioacchino.delregno@...labora.com>, "robh@...nel.org"
<robh@...nel.org>, Jason-JH Lin (林睿祥)
<Jason-JH.Lin@...iatek.com>, "krzk+dt@...nel.org" <krzk+dt@...nel.org>,
"jassisinghbrar@...il.com" <jassisinghbrar@...il.com>, "mchehab@...nel.org"
<mchehab@...nel.org>, "matthias.bgg@...il.com" <matthias.bgg@...il.com>,
"conor+dt@...nel.org" <conor+dt@...nel.org>
CC: "linux-media@...r.kernel.org" <linux-media@...r.kernel.org>,
Singo Chang (張興國) <Singo.Chang@...iatek.com>,
"simona@...ll.ch" <simona@...ll.ch>, Moudy Ho (何宗原)
<Moudy.Ho@...iatek.com>, "dri-devel@...ts.freedesktop.org"
<dri-devel@...ts.freedesktop.org>, "devicetree@...r.kernel.org"
<devicetree@...r.kernel.org>, "linux-kernel@...r.kernel.org"
<linux-kernel@...r.kernel.org>, "airlied@...il.com" <airlied@...il.com>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
Xavier Chang (張獻文) <Xavier.Chang@...iatek.com>,
"linux-mediatek@...ts.infradead.org" <linux-mediatek@...ts.infradead.org>,
Nancy Lin (林欣螢) <Nancy.Lin@...iatek.com>,
Project_Global_Chrome_Upstream_Group
<Project_Global_Chrome_Upstream_Group@...iatek.com>
Subject: Re: [PATCH v2 7/8] drm/mediatek: Add programming flow for unsupported
subsys ID hardware
Hi, Jason:
On Wed, 2024-12-11 at 11:22 +0800, Jason-JH.Lin wrote:
> To support hardware without subsys IDs on new SoCs, add a programming
> flow that checks whether the subsys ID is valid. If the subsys ID is
> invalid, the flow will call 2 alternative CMDQ APIs:
> cmdq_pkt_assign() and cmdq_pkt_write_s_value() to achieve the same
> functionality.
>
> Signed-off-by: Jason-JH.Lin <jason-jh.lin@...iatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 34 ++++++++++++++++++++-----
> 1 file changed, 28 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> index edc6417639e6..0792c895526f 100644
> --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> @@ -66,14 +66,38 @@ struct mtk_ddp_comp_dev {
> struct cmdq_client_reg cmdq_reg;
> };
>
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> +static void mtk_ddp_write_cmdq_pkt(struct cmdq_pkt *cmdq_pkt, struct cmdq_client_reg *cmdq_reg,
> + unsigned int offset, unsigned int value, unsigned int mask)
Drop this function.
> +{
> + struct cmdq_client *cl = (struct cmdq_client *)cmdq_pkt->cl;
> +
> + offset += cmdq_reg->offset;
> +
> + if (cmdq_subsys_is_valid(cl->chan, cmdq_reg->subsys)) {
> + if (mask == GENMASK(31, 0))
> + cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys, offset, value);
> + else
> + cmdq_pkt_write_mask(cmdq_pkt, cmdq_reg->subsys, offset, value, mask);
> + } else {
> + /* only MMIO access, no need to check mminfro_offset */
> + cmdq_pkt_assign(cmdq_pkt, 0, CMDQ_ADDR_HIGH(cmdq_reg->pa_base));
> + if (mask == GENMASK(31, 0))
> + cmdq_pkt_write_s_value(cmdq_pkt, 0, CMDQ_ADDR_LOW(offset), value);
> + else
> + cmdq_pkt_write_s_mask_value(cmdq_pkt, 0, CMDQ_ADDR_LOW(offset),
> + value, mask);
> + }
> +}
> +#endif
> +
> void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value,
> struct cmdq_client_reg *cmdq_reg, void __iomem *regs,
> unsigned int offset)
> {
> #if IS_REACHABLE(CONFIG_MTK_CMDQ)
> if (cmdq_pkt)
> - cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys,
> - cmdq_reg->offset + offset, value);
> + mtk_ddp_write_cmdq_pkt(cmdq_pkt, cmdq_reg, offset, value, GENMASK(31, 0));
/* only MMIO access, no need to check mminfro_offset */
cmdq_pkt_assign(cmdq_pkt, CMDQ_XXXREG_0, CMDQ_ADDR_HIGH(cmdq_reg->pa_base));
cmdq_pkt_write_s_value(cmdq_pkt, CMDQ_XXXREG_0, CMDQ_ADDR_LOW(offset), value);
> else
> #endif
> writel(value, regs + offset);
> @@ -85,8 +109,7 @@ void mtk_ddp_write_relaxed(struct cmdq_pkt *cmdq_pkt, unsigned int value,
> {
> #if IS_REACHABLE(CONFIG_MTK_CMDQ)
> if (cmdq_pkt)
> - cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys,
> - cmdq_reg->offset + offset, value);
> + mtk_ddp_write_cmdq_pkt(cmdq_pkt, cmdq_reg, offset, value, GENMASK(31, 0));
/* only MMIO access, no need to check mminfro_offset */
cmdq_pkt_assign(cmdq_pkt, CMDQ_XXXREG_0, CMDQ_ADDR_HIGH(cmdq_reg->pa_base));
cmdq_pkt_write_s_value(cmdq_pkt, CMDQ_XXXREG_0, CMDQ_ADDR_LOW(offset), value);
> else
> #endif
> writel_relaxed(value, regs + offset);
> @@ -98,8 +121,7 @@ void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, unsigned int value,
> {
> #if IS_REACHABLE(CONFIG_MTK_CMDQ)
> if (cmdq_pkt) {
> - cmdq_pkt_write_mask(cmdq_pkt, cmdq_reg->subsys,
> - cmdq_reg->offset + offset, value, mask);
> + mtk_ddp_write_cmdq_pkt(cmdq_pkt, cmdq_reg, offset, value, mask);
/* only MMIO access, no need to check mminfro_offset */
cmdq_pkt_assign(cmdq_pkt, CMDQ_XXXREG_0, CMDQ_ADDR_HIGH(cmdq_reg->pa_base));
cmdq_pkt_write_s_mask_value(cmdq_pkt, CMDQ_XXXREG_0, CMDQ_ADDR_LOW(offset),
value, mask);
CMDQ_XXXREG_0 is defined in cmdq header file.
Regards,
CK
> } else {
> #endif
> u32 tmp = readl(regs + offset);
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