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Message-ID: <8395fb6b-d7a5-4e2c-9eb3-4984b8c775c4@lunn.ch>
Date: Wed, 11 Dec 2024 14:45:46 +0100
From: Andrew Lunn <andrew@...n.ch>
To: Michal Simek <michal.simek@....com>
Cc: linux-kernel@...r.kernel.org, monstr@...str.eu, michal.simek@...inx.com,
git@...inx.com, Conor Dooley <conor+dt@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Rob Herring <robh@...nel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" <devicetree@...r.kernel.org>,
"moderated list:ARM/ZYNQ ARCHITECTURE" <linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH 07/15] ARM: zynq: Add ethernet phy reset information to
DT(zc702)
On Wed, Dec 11, 2024 at 01:41:26PM +0100, Michal Simek wrote:
> Added phy reset gpio information for gem0.
>
> Signed-off-by: Michal Simek <michal.simek@....com>
> ---
>
> arch/arm/boot/dts/xilinx/zynq-zc702.dts | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm/boot/dts/xilinx/zynq-zc702.dts b/arch/arm/boot/dts/xilinx/zynq-zc702.dts
> index 424e78f6c148..975385f4ac01 100644
> --- a/arch/arm/boot/dts/xilinx/zynq-zc702.dts
> +++ b/arch/arm/boot/dts/xilinx/zynq-zc702.dts
> @@ -79,6 +79,8 @@ &gem0 {
> phy-handle = <ðernet_phy>;
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_gem0_default>;
> + phy-reset-gpio = <&gpio0 11 0>;
> + phy-reset-active-low;
Hi Michal
Could you point me at code which actually implements these two
properties.
What is more normal is a reset-gpios property in the PHY node, or a
reset-gpios in the MDIO node.
Andrew
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