linux-kernel - Re: [PATCH 0/8] x86, sched: Dynamic ITMT core ranking support and some yak shaving

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Message-ID: <b46e17c601fbea5c10b2d1674c6d5799bad17ddf.camel@linux.intel.com>
Date: Fri, 13 Dec 2024 13:11:44 -0800
From: Tim Chen <tim.c.chen@...ux.intel.com>
To: K Prateek Nayak <kprateek.nayak@....com>, Thomas Gleixner
 <tglx@...utronix.de>, Ingo Molnar <mingo@...hat.com>, Borislav Petkov
 <bp@...en8.de>, Dave Hansen <dave.hansen@...ux.intel.com>, Peter Zijlstra
 <peterz@...radead.org>, Juri Lelli <juri.lelli@...hat.com>, Vincent Guittot
 <vincent.guittot@...aro.org>, x86@...nel.org, linux-kernel@...r.kernel.org
Cc: "H. Peter Anvin" <hpa@...or.com>, Dietmar Eggemann
 <dietmar.eggemann@....com>, Steven Rostedt <rostedt@...dmis.org>, Ben
 Segall <bsegall@...gle.com>, Mel Gorman <mgorman@...e.de>, Valentin
 Schneider <vschneid@...hat.com>, "Rafael J. Wysocki"
 <rafael.j.wysocki@...el.com>,  Ricardo Neri
 <ricardo.neri-calderon@...ux.intel.com>, Mario Limonciello
 <mario.limonciello@....com>,  Meng Li <li.meng@....com>, Huang Rui
 <ray.huang@....com>, "Gautham R. Shenoy" <gautham.shenoy@....com>, Srinivas
 Pandruvada <srinivas.pandruvada@...ux.intel.com>
Subject: Re: [PATCH 0/8] x86, sched: Dynamic ITMT core ranking support and
 some yak shaving

On Fri, 2024-12-13 at 09:42 +0530, K Prateek Nayak wrote:
> Hello Tim,
> 
> On 12/13/2024 6:03 AM, Tim Chen wrote:
> > On Wed, 2024-12-11 at 18:55 +0000, K Prateek Nayak wrote:
> > > The ITMT infrastructure currently assumes ITMT rankings to be static and
> > > is set correctly prior to enabling ITMT support which allows the CPU
> > > with the highest core ranking to be cached as the "asym_prefer_cpu" in
> > > the sched_group struct. However, with the introduction of Preferred Core
> > > support in amd-pstate, these rankings can change at runtime.
> > > 
> > > This series adds support for dynamic ranking in generic scheduler layer
> > > without the need to rebuild the sched domain hierarchy and fixes an
> > > issue with x86_die_flags() on AMD systems that support Preferred Core
> > > ranking with some yak shaving done along the way.
> > > 
> > > Patch 1 to 4 are independent cleanup around ITMT infrastructure, removal
> > > of x86_smt_flags wrapper, and moving the "sched_itmt_enabled" sysctl to
> > > debugfs.
> > > 
> > > Patch 5 adds the SD_ASYM_PACKING flag to the PKG domain on all ITMT
> > > enabled systems. The rationale behind the addition is elaborates in the
> > > same. One open question remains is for Intel processors with multiple
> > > Tiles in a PKG which advertises itself as multiple LLCs in a PKG and
> > > supports ITMT - is it okay to set SD_ASYM_PACKING for PKG domain on
> > > these processors?
> > 
> > After talking to my colleagues Ricardo and Srinivas, we think that this
> > should be fine for Intel CPUs.
> 
> Thank you for confirming that. Could you also confirm if my observations
> for Intel systems on Patch 5 covered all possible scenarios for the ones
> that feature multiple MC groups within a PKG and enable ITMT support. If
> I'm missing something, please do let me know and we can hash out the
> implementation details.

Your patch 5 implementation should be fine as far as we can tell.

Tim
> 
> Thanks a ton for reviewing the series!
>