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Message-Id: <20241214143039.4139398-1-guoren@kernel.org> Date: Sat, 14 Dec 2024 09:30:37 -0500 From: guoren@...nel.org To: guoren@...nel.org, conor@...nel.org, alexghiti@...osinc.com Cc: linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org, paul.walmsley@...ive.com, palmer@...belt.com, bjorn@...osinc.com, leobras@...hat.com, corbet@....net, peterlin@...estech.com, Guo Ren <guoren@...ux.alibaba.com> Subject: [PATCH 0/2] riscv: qspinlock: errata: Add ERRATA_THEAD_WRITE_ONCE fixup From: Guo Ren <guoren@...ux.alibaba.com> The early version of T-Head C9xx cores has a store merge buffer delay problem. The store merge buffer could improve the store queue performance by merging multi-store requests, but when there are not continued store requests, the prior single store request would be waiting in the store queue for a long time. That would cause significant problems for communication between multi-cores. This problem was found on sg2042 & th1520 platforms with the qspinlock lock torture test. The orignal patch is from: https://lore.kernel.org/linux-riscv/20231225125847.2778638-5-guoren@kernel.org/ Guo Ren (2): riscv: Move vendor errata definitions into vendorid_list.h riscv: qspinlock: errata: Add ERRATA_THEAD_WRITE_ONCE fixup arch/riscv/Kconfig.errata | 19 +++++++++++++++ arch/riscv/errata/thead/errata.c | 20 ++++++++++++++++ arch/riscv/include/asm/errata_list.h | 17 ------------- arch/riscv/include/asm/rwonce.h | 33 ++++++++++++++++++++++++++ arch/riscv/include/asm/vendorid_list.h | 18 ++++++++++++++ include/asm-generic/rwonce.h | 2 ++ 6 files changed, 92 insertions(+), 17 deletions(-) create mode 100644 arch/riscv/include/asm/rwonce.h -- 2.40.1
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