linux-kernel - Re: [PATCH 1/4] dt-bindings: net: Add Realtek MDIO controller

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Message-ID: <bd481a13-73a3-4325-8e16-ea2b2c6b0f6e@alliedtelesis.co.nz>
Date: Mon, 16 Dec 2024 08:52:07 +1300
From: Chris Packham <chris.packham@...iedtelesis.co.nz>
To: Andrew Lunn <andrew@...n.ch>
Cc: lee@...nel.org, robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
 andrew+netdev@...n.ch, davem@...emloft.net, edumazet@...gle.com,
 kuba@...nel.org, pabeni@...hat.com, tsbogend@...ha.franken.de,
 hkallweit1@...il.com, linux@...linux.org.uk, markus.stockhausen@....de,
 devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
 netdev@...r.kernel.org, linux-mips@...r.kernel.org
Subject: Re: [PATCH 1/4] dt-bindings: net: Add Realtek MDIO controller

Hi Andrew,

On 14/12/2024 00:58, Andrew Lunn wrote:
> On Fri, Dec 13, 2024 at 01:56:52PM +1300, Chris Packham wrote:
>> Hi Andrew,
>>
>> On 13/12/2024 06:13, Andrew Lunn wrote:
>>>> +      realtek,smi-address:
>>>> +        $ref: /schemas/types.yaml#/definitions/uint32-array
>>>> +        description: SMI interface and address for the connected PHY
>>>> +        items:
>>>> +          - description: SMI interface number associated with the port.
>>>> +          - description: SMI address of the PHY for the port.
>>> Is the hardware really random here with its mapping of PHYs?
>>> Generally, hardware is pretty predictable, logical. I'm just wondering
>>> if this property is really required, or if it can be replaced with
>>> some logic, avoiding typ0s.
>> The hardware is pretty flexible in this respect. You can pretty arbitrarily
>> arrange your PHYs. Not all ports support the same kind of SERDES interface
>> but as far as the MDIO interface goes you can arrange things however you
>> like.
> Is there a reason to not just statically define it, maybe with a table
> in the driver? Does a DT developer actually need this flexibility?

It's a part of the board design so I think it's something that should go 
into the device tree. For example I've got 3 different boards right now 
that use different arrangements of MDIO connections to the PHYs mostly 
for ease of board layout (and one because it has different PHYs).