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Message-ID: <173445353302.470882.8616229131234263005.b4-ty@kernel.org>
Date: Tue, 17 Dec 2024 10:38:54 -0600
From: Bjorn Andersson <andersson@...nel.org>
To: konradybcio@...nel.org,
	robh@...nel.org,
	krzk+dt@...nel.org,
	conor+dt@...nel.org,
	Qiang Yu <quic_qianyu@...cinc.com>
Cc: johan@...nel.org,
	linux-arm-msm@...r.kernel.org,
	devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	quic_cang@...cinc.com,
	quic_mrana@...cinc.com,
	stable@...r.kernel.org
Subject: Re: (subset) [PATCH 1/1] arm64: dts: qcom: x1e80100: Fix up BAR space size for PCIe6a


On Wed, 13 Nov 2024 00:05:08 -0800, Qiang Yu wrote:
> As per memory map table, the region for PCIe6a is 64MByte. Hence, set the
> size of 32 bit non-prefetchable memory region beginning on address
> 0x70300000 as 0x3d00000 so that BAR space assigned to BAR registers can be
> allocated from 0x70300000 to 0x74000000.
> 
> 

Applied, thanks!

[1/1] arm64: dts: qcom: x1e80100: Fix up BAR space size for PCIe6a
      commit: fb8e7b33c2174e00dfa411361eeed21eeaf3634b

Best regards,
-- 
Bjorn Andersson <andersson@...nel.org>

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