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Message-ID: <2c0e701d9fcf69090daf8c4087c87d2a.sboyd@kernel.org>
Date: Tue, 17 Dec 2024 12:18:15 -0800
From: Stephen Boyd <sboyd@...nel.org>
To: bigunclemax@...il.com
Cc: bigunclemax@...il.com, Drew Fustini <drew@...7.com>, Guo Ren <guoren@...nel.org>, Fu Wei <wefu@...hat.com>, Michael Turquette <mturquette@...libre.com>, Yangtao Li <frank.li@...o.com>, Jisheng Zhang <jszhang@...nel.org>, linux-riscv@...ts.infradead.org, linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2] clk: thead: Fix TH1520 emmc and shdci clock rate

Quoting bigunclemax@...il.com (2024-12-10 00:30:27)
> From: Maksim Kiselev <bigunclemax@...il.com>
> 
> In accordance with LicheePi 4A BSP the clock that comes to emmc/sdhci
> is 198Mhz which is got through frequency division of source clock
> VIDEO PLL by 4 [1].
> 
> But now the AP_SUBSYS driver sets the CLK EMMC SDIO to the same
> frequency as the VIDEO PLL, equal to 792 MHz. This causes emmc/sdhci
> to work 4 times slower.
> 
> Let's fix this issue by adding fixed factor clock that divides
> VIDEO PLL by 4 for emmc/sdhci.
> 
> Link: https://github.com/revyos/thead-kernel/blob/7563179071a314f41cdcdbfd8cf6e101e73707f3/drivers/clk/thead/clk-light-fm.c#L454
> 
> Fixes: ae81b69fd2b1 ("clk: thead: Add support for T-Head TH1520 AP_SUBSYS clocks")
> Signed-off-by: Maksim Kiselev <bigunclemax@...il.com>
> ---

Applied to clk-fixes

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