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Message-ID: <Z2WVCyJbJTpU/FrY@lizhi-Precision-Tower-5810>
Date: Fri, 20 Dec 2024 11:02:19 -0500
From: Frank Li <Frank.li@....com>
To: Ciprian Costea <ciprianmarian.costea@....nxp.com>
Cc: Chester Lin <chester62515@...il.com>,
Matthias Brugger <mbrugger@...e.com>,
Ghennadi Procopciuc <ghennadi.procopciuc@....nxp.com>,
Shawn Guo <shawnguo@...nel.org>,
Sascha Hauer <s.hauer@...gutronix.de>,
Fabio Estevam <festevam@...il.com>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
linux-arm-kernel@...ts.infradead.org, imx@...ts.linux.dev,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
NXP S32 Linux <s32@....com>, Christophe Lizzi <clizzi@...hat.com>,
Alberto Ruiz <aruizrui@...hat.com>,
Enric Balletbo <eballetb@...hat.com>
Subject: Re: [PATCH v4 2/4] arm64: dts: s32g: add common 'S32G-EVB' and
'S32G-RDB' board support
On Fri, Dec 20, 2024 at 02:39:14PM +0200, Ciprian Costea wrote:
> From: Ciprian Marian Costea <ciprianmarian.costea@....nxp.com>
>
> With respect to S32G2/S32G3 SoC based boards, there are multiple RDB
> (rdb2 vs rdb3) and EVB (for G2 vs for G3) board revisions. These versions
> are quite similar. The common part for the EVB revisions will be
> centralized in 's32gxxa-evb.dtsi' file, while the RDB commonalities will
> be placed in 's32gxxa-rdb.dtsi' file.
>
> This refactor will also serve for other modules in the future, such as
> FlexCAN, DSPI.
https://docs.kernel.org/process/submitting-patches.html
"Describe your changes in imperative mood, e.g. “make xyzzy do frotz”
instead of “[This patch] makes xyzzy do frotz” or “[I] changed xyzzy to do
frotz”, as if you are giving orders to the codebase to change its
behaviour."
So suggest..
Create common part, s32gxxa-evb.dtsi and s32gxxa-rdb.dtsi, for S32G2/S32G3
RDB2\3 and EVB G2/G3 boards to avoid copy duplicate part in boards dts
file. Prepare to add other modules easily in the future.
>
> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@....nxp.com>
> ---
> .../boot/dts/freescale/s32gxxxa-evb.dtsi | 150 ++++++++++++++++++
> .../boot/dts/freescale/s32gxxxa-rdb.dtsi | 122 ++++++++++++++
> 2 files changed, 272 insertions(+)
> create mode 100644 arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
> create mode 100644 arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi
I think you should squash patch 3/4 to this one. All is for the boards dts.
Frank
>
> diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
> new file mode 100644
> index 000000000000..a44eff28073a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
> @@ -0,0 +1,150 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> +/*
> + * Copyright 2024 NXP
> + *
> + * Authors: Ciprian Marian Costea <ciprianmarian.costea@....nxp.com>
> + * Ghennadi Procopciuc <ghennadi.procopciuc@....nxp.com>
> + * Larisa Grigore <larisa.grigore@....com>
> + */
> +
> +&pinctrl {
> + i2c0_pins: i2c0-pins {
> + i2c0-grp0 {
> + pinmux = <0x101>, <0x111>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c0-grp1 {
> + pinmux = <0x2352>, <0x2362>;
> + };
> + };
> +
> + i2c0_gpio_pins: i2c0-gpio-pins {
> + i2c0-gpio-grp0 {
> + pinmux = <0x100>, <0x110>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c0-gpio-grp1 {
> + pinmux = <0x2350>, <0x2360>;
> + };
> + };
> +
> + i2c1_pins: i2c1-pins {
> + i2c1-grp0 {
> + pinmux = <0x131>, <0x141>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c1-grp1 {
> + pinmux = <0x2cd2>, <0x2ce2>;
> + };
> + };
> +
> + i2c1_gpio_pins: i2c1-gpio-pins {
> + i2c1-gpio-grp0 {
> + pinmux = <0x130>, <0x140>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c1-gpio-grp1 {
> + pinmux = <0x2cd0>, <0x2ce0>;
> + };
> + };
> +
> + i2c2_pins: i2c2-pins {
> + i2c2-grp0 {
> + pinmux = <0x151>, <0x161>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c2-grp1 {
> + pinmux = <0x2cf2>, <0x2d02>;
> + };
> + };
> +
> + i2c2_gpio_pins: i2c2-gpio-pins {
> + i2c2-gpio-grp0 {
> + pinmux = <0x150>, <0x160>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c2-gpio-grp1 {
> + pinmux = <0x2cf0>, <0x2d00>;
> + };
> + };
> +
> + i2c4_pins: i2c4-pins {
> + i2c4-grp0 {
> + pinmux = <0x211>, <0x222>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c4-grp1 {
> + pinmux = <0x2d43>, <0x2d33>;
> + };
> + };
> +
> + i2c4_gpio_pins: i2c4-gpio-pins {
> + i2c4-gpio-grp0 {
> + pinmux = <0x210>, <0x220>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c4-gpio-grp1 {
> + pinmux = <0x2d40>, <0x2d30>;
> + };
> + };
> +};
> +
> +&i2c0 {
> + pinctrl-names = "default", "gpio";
> + pinctrl-0 = <&i2c0_pins>;
> + pinctrl-1 = <&i2c0_gpio_pins>;
> + status = "okay";
> +};
> +
> +&i2c1 {
> + pinctrl-names = "default", "gpio";
> + pinctrl-0 = <&i2c1_pins>;
> + pinctrl-1 = <&i2c1_gpio_pins>;
> + status = "okay";
> +};
> +
> +&i2c2 {
> + pinctrl-names = "default", "gpio";
> + pinctrl-0 = <&i2c2_pins>;
> + pinctrl-1 = <&i2c2_gpio_pins>;
> + status = "okay";
> +};
> +
> +&i2c4 {
> + pinctrl-names = "default", "gpio";
> + pinctrl-0 = <&i2c4_pins>;
> + pinctrl-1 = <&i2c4_gpio_pins>;
> + status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi
> new file mode 100644
> index 000000000000..91fd8dbf2224
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi
> @@ -0,0 +1,122 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> +/*
> + * Copyright 2024 NXP
> + *
> + * Authors: Ciprian Marian Costea <ciprianmarian.costea@....nxp.com>
> + * Ghennadi Procopciuc <ghennadi.procopciuc@....nxp.com>
> + * Larisa Grigore <larisa.grigore@....com>
> + */
> +
> +&pinctrl {
> + i2c0_pins: i2c0-pins {
> + i2c0-grp0 {
> + pinmux = <0x1f2>, <0x201>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c0-grp1 {
> + pinmux = <0x2353>, <0x2363>;
> + };
> + };
> +
> + i2c0_gpio_pins: i2c0-gpio-pins {
> + i2c0-gpio-grp0 {
> + pinmux = <0x1f0>, <0x200>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c0-gpio-grp1 {
> + pinmux = <0x2350>, <0x2360>;
> + };
> + };
> +
> + i2c2_pins: i2c2-pins {
> + i2c2-grp0 {
> + pinmux = <0x151>, <0x161>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c2-grp1 {
> + pinmux = <0x2cf2>, <0x2d02>;
> + };
> + };
> +
> + i2c2_gpio_pins: i2c2-gpio-pins {
> + i2c2-gpio-grp0 {
> + pinmux = <0x2cf0>, <0x2d00>;
> + };
> +
> + i2c2-gpio-grp1 {
> + pinmux = <0x150>, <0x160>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> + };
> +
> + i2c4_pins: i2c4-pins {
> + i2c4-grp0 {
> + pinmux = <0x211>, <0x222>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c4-grp1 {
> + pinmux = <0x2d43>, <0x2d33>;
> + };
> + };
> +
> + i2c4_gpio_pins: i2c4-gpio-pins {
> + i2c4-gpio-grp0 {
> + pinmux = <0x210>, <0x220>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c4-gpio-grp1 {
> + pinmux = <0x2d40>, <0x2d30>;
> + };
> + };
> +};
> +
> +&i2c0 {
> + pinctrl-names = "default", "gpio";
> + pinctrl-0 = <&i2c0_pins>;
> + pinctrl-1 = <&i2c0_gpio_pins>;
> + status = "okay";
> +
> + pcal6524: gpio-expander@22 {
> + compatible = "nxp,pcal6524";
> + reg = <0x22>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + };
> +};
> +
> +&i2c2 {
> + pinctrl-names = "default", "gpio";
> + pinctrl-0 = <&i2c2_pins>;
> + pinctrl-1 = <&i2c2_gpio_pins>;
> + status = "okay";
> +};
> +
> +&i2c4 {
> + pinctrl-names = "default", "gpio";
> + pinctrl-0 = <&i2c4_pins>;
> + pinctrl-1 = <&i2c4_gpio_pins>;
> + status = "okay";
> +};
> --
> 2.45.2
>
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