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Message-ID: <CAGQJe6oBqt-O5c_+pG7P6AQQ4wGsi4g0ig9O7N4nPcCXCaQ4sA@mail.gmail.com>
Date: Fri, 27 Dec 2024 15:01:33 +0100
From: Aleksandar Rikalo <arikalo@...il.com>
To: Olof Johansson <olof@...om.net>
Cc: linux-riscv@...ts.infradead.org, Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>,
Andrew Jones <ajones@...tanamicro.com>,
Christoph Müllner <christoph.muellner@...ll.eu>,
linux-kernel@...r.kernel.org,
Djordje Todorovic <djordje.todorovic@...cgroup.com>
Subject: Re: [PATCH] riscv: Fix the PAUSE Opcode for MIPS P8700.
On Thu, Dec 19, 2024 at 7:46 PM Olof Johansson <olof@...om.net> wrote:
>
> On Wed, Dec 18, 2024 at 02:33:40PM +0100, Aleksandar Rikalo wrote:
> > From: Raj Vishwanathan4 <rvishwanathan@...s.com>
> >
> > The riscv MIPS P8700 uses a different opcode for PAUSE.
> > It is a ‘hint’ encoding of the SLLI instruction, with rd=0, rs1=0 and
> > imm=5. It will behave as a NOP instruction if no additional behavior
> > beyond that of SLLI is implemented.
> >
> > Signed-off-by: Raj Vishwanathan4 <rvishwanathan@...s.com>
> > Signed-off-by: Aleksandar Rikalo <arikalo@...il.com>
> > ---
> > arch/riscv/Kconfig | 12 ++++++++++++
> > arch/riscv/include/asm/insn-def.h | 5 +++++
> > 2 files changed, 17 insertions(+)
> >
> This means that a kernel that's built for MIPS P8700 won't do the right
> thing on other platforms, i.e. single platform builds. That's not the
> right approach.
>
> It would make more sense to treat this as an errata with boot time
> patchup.
>
> -Olof
We did it that way in version 2. Please see:
https://lore.kernel.org/linux-riscv/20241227135832.188256-1-arikalo@gmail.com
-- Aleksandar
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