linux-kernel - [PATCH v4 4/4] riscv: dts: spacemit: Add clock controller for K1

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Message-ID: <20250103215636.19967-6-heylenay@4d2.org>
Date: Fri,  3 Jan 2025 21:56:37 +0000
From: Haylen Chu <heylenay@....org>
To: Michael Turquette <mturquette@...libre.com>,
	Stephen Boyd <sboyd@...nel.org>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Haylen Chu <heylenay@...look.com>,
	Yixun Lan <dlan@...too.org>
Cc: linux-riscv@...ts.infradead.org,
	linux-clk@...r.kernel.org,
	devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	Inochi Amaoto <inochiama@...look.com>,
	Chen Wang <unicornxdotw@...mail.com>,
	Jisheng Zhang <jszhang@...nel.org>,
	Meng Zhang <zhangmeng.kevin@...ux.spacemit.com>,
	Haylen Chu <heylenay@....org>
Subject: [PATCH v4 4/4] riscv: dts: spacemit: Add clock controller for K1

Add clock controllers for APBC, APBS, APMU and MPMU regions along with
system controllers which they belong to.

Signed-off-by: Haylen Chu <heylenay@....org>
---
 arch/riscv/boot/dts/spacemit/k1.dtsi | 97 ++++++++++++++++++++++++++++
 1 file changed, 97 insertions(+)

diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
index 0777bf9e0118..a2cd141f9177 100644
--- a/arch/riscv/boot/dts/spacemit/k1.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
@@ -3,6 +3,8 @@
  * Copyright (C) 2024 Yangyu Chen <cyy@...self.name>
  */
 
+#include <dt-bindings/clock/spacemit,k1-ccu.h>
+
 /dts-v1/;
 / {
 	#address-cells = <2>;
@@ -318,6 +320,40 @@ cluster1_l2_cache: l2-cache1 {
 		};
 	};
 
+	clocks {
+		#address-cells = <0x2>;
+		#size-cells = <0x2>;
+		ranges;
+
+		vctcxo_1m: clock-1m {
+			compatible = "fixed-clock";
+			clock-frequency = <1000000>;
+			clock-output-names = "vctcxo_1m";
+			#clock-cells = <0>;
+		};
+
+		vctcxo_24m: clock-24m {
+			compatible = "fixed-clock";
+			clock-frequency = <24000000>;
+			clock-output-names = "vctcxo_24m";
+			#clock-cells = <0>;
+		};
+
+		vctcxo_3m: clock-3m {
+			compatible = "fixed-clock";
+			clock-frequency = <3000000>;
+			clock-output-names = "vctcxo_3m";
+			#clock-cells = <0>;
+		};
+
+		osc_32k: clock-32k {
+			compatible = "fixed-clock";
+			clock-frequency = <32000>;
+			clock-output-names = "osc_32k";
+			#clock-cells = <0>;
+		};
+	};
+
 	soc {
 		compatible = "simple-bus";
 		interrupt-parent = <&plic>;
@@ -326,6 +362,21 @@ soc {
 		dma-noncoherent;
 		ranges;
 
+		syscon_apbc: system-control@...15000 {
+			compatible = "spacemit,k1-apbc-syscon", "syscon",
+				     "simple-mfd";
+			reg = <0x0 0xd4015000 0x0 0x1000>;
+
+			clk_apbc: clock-controller {
+				compatible = "spacemit,k1-ccu-apbc";
+				clocks = <&osc_32k>, <&vctcxo_1m>,
+					 <&vctcxo_3m>, <&vctcxo_24m>;
+				clock-names = "osc", "vctcxo_1m",
+					      "vctcxo_3m", "vctcxo_24m";
+				#clock-cells = <1>;
+			};
+		};
+
 		uart0: serial@...17000 {
 			compatible = "spacemit,k1-uart", "intel,xscale-uart";
 			reg = <0x0 0xd4017000 0x0 0x100>;
@@ -416,6 +467,52 @@ uart9: serial@...17800 {
 			status = "disabled";
 		};
 
+		syscon_mpmu: system-control@...50000 {
+			compatible = "spacemit,k1-mpmu-syscon", "syscon",
+				     "simple-mfd";
+			reg = <0x0 0xd4050000 0x0 0x209c>;
+
+			clk_mpmu: clock-controller {
+				compatible = "spacemit,k1-ccu-mpmu";
+				clocks = <&osc_32k>, <&vctcxo_1m>,
+					 <&vctcxo_3m>, <&vctcxo_24m>;
+				clock-names = "osc", "vctcxo_1m",
+					      "vctcxo_3m", "vctcxo_24m";
+				#clock-cells = <1>;
+			};
+		};
+
+		syscon_apbs: system-control@...90000 {
+			compatible = "spacemit,k1-apbs-syscon", "syscon",
+				     "simple-mfd";
+			reg = <0x0 0xd4090000 0x0 0x1000>;
+
+			clk_apbs: clock-controller {
+				compatible = "spacemit,k1-ccu-apbs";
+				clocks = <&osc_32k>, <&vctcxo_1m>,
+					 <&vctcxo_3m>, <&vctcxo_24m>;
+				clock-names = "osc", "vctcxo_1m",
+					      "vctcxo_3m", "vctcxo_24m";
+				spacemit,mpmu = <&syscon_mpmu>;
+				#clock-cells = <1>;
+			};
+		};
+
+		syscon_apmu: system-control@...82800 {
+			compatible = "spacemit,k1-apmu-syscon", "syscon",
+				     "simple-mfd";
+			reg = <0x0 0xd4282800 0x0 0x400>;
+
+			clk_apmu: clock-controller {
+				compatible = "spacemit,k1-ccu-apmu";
+				clocks = <&osc_32k>, <&vctcxo_1m>,
+					 <&vctcxo_3m>, <&vctcxo_24m>;
+				clock-names = "osc", "vctcxo_1m",
+					      "vctcxo_3m", "vctcxo_24m";
+				#clock-cells = <1>;
+			};
+		};
+
 		plic: interrupt-controller@...00000 {
 			compatible = "spacemit,k1-plic", "sifive,plic-1.0.0";
 			reg = <0x0 0xe0000000 0x0 0x4000000>;
-- 
2.47.1