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Message-ID: <Z3eJQyJXSBG+oFF4@hu-varada-blr.qualcomm.com>
Date: Fri, 3 Jan 2025 12:22:51 +0530
From: Varadarajan Narayanan <quic_varada@...cinc.com>
To: Manikanta Mylavarapu <quic_mmanikan@...cinc.com>
CC: <bhelgaas@...gle.com>, <lpieralisi@...nel.org>, <kw@...ux.com>,
<manivannan.sadhasivam@...aro.org>, <robh@...nel.org>,
<krzk+dt@...nel.org>, <conor+dt@...nel.org>, <vkoul@...nel.org>,
<kishon@...nel.org>, <andersson@...nel.org>, <konradybcio@...nel.org>,
<linux-arm-msm@...r.kernel.org>, <linux-pci@...r.kernel.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-phy@...ts.infradead.org>, <quic_srichara@...cinc.com>
Subject: Re: [PATCH 4/4] arm64: dts: qcom: ipq5424: Enable PCIe PHYs and
controllers
On Fri, Dec 13, 2024 at 07:19:50PM +0530, Manikanta Mylavarapu wrote:
[ . . . ]
> +&pcie2_phy {
> + status = "okay";
> +};
> +
> +&pcie2 {
> + pinctrl-0 = <&pcie2_default_state>;
> + pinctrl-names = "default";
> +
> + perst-gpios = <&tlmm 31 GPIO_ACTIVE_LOW>;
> + status = "okay";
> +};
pcie2 should come before pcie2_phy
> +
> +&pcie3_phy {
> + status = "okay";
> +};
> +
> +&pcie3 {
> + pinctrl-0 = <&pcie3_default_state>;
> + pinctrl-names = "default";
> +
> + perst-gpios = <&tlmm 34 GPIO_ACTIVE_LOW>;
> + status = "okay";
> +};
same here.
-Varada
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