linux-kernel - Re: [PATCH v2 1/2] phy: cadence-torrent: Add PCIe multilink configuration for 100 MHz refclk

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Message-ID: <1483780d-115f-4555-82b3-3e9cffe82dce@wanadoo.fr>
Date: Mon, 6 Jan 2025 23:00:14 +0100
From: Christophe JAILLET <christophe.jaillet@...adoo.fr>
To: Siddharth Vadapalli <s-vadapalli@...com>, vkoul@...nel.org,
 kishon@...nel.org, sjakhade@...ence.com, rogerq@...nel.org,
 thomas.richard@...tlin.com, u.kleine-koenig@...libre.com, eballetb@...hat.com
Cc: linux-phy@...ts.infradead.org, linux-kernel@...r.kernel.org,
 linux-arm-kernel@...ts.infradead.org, srk@...com
Subject: Re: [PATCH v2 1/2] phy: cadence-torrent: Add PCIe multilink
 configuration for 100 MHz refclk

Le 06/01/2025 à 14:19, Siddharth Vadapalli a écrit :
> From: Swapnil Jakhade <sjakhade@...ence.com>
> 
> Add register sequences to support PCIe multilink configuration for 100MHz
> reference clock. Maximum two PCIe links are supported.
> 
> Signed-off-by: Swapnil Jakhade <sjakhade@...ence.com>
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@...com>
> ---
> 
> ***NOTE***
> Since I don't have the hardware required to validate PCIe Multilink +
> USB functionality, kindly *do not merge* this series until it gets a
> "Tested-by" tag with proper validation of the functionality.
> 
> Regards,
> Siddharth.
> 
>   drivers/phy/cadence/phy-cadence-torrent.c | 130 +++++++++++++++++++++-
>   1 file changed, 129 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c
> index a281c0dfae97..b0b5f4bdd7e2 100644
> --- a/drivers/phy/cadence/phy-cadence-torrent.c
> +++ b/drivers/phy/cadence/phy-cadence-torrent.c
> @@ -197,6 +197,7 @@
>   #define RX_SDCAL1_INIT_TMR		0x004CU
>   #define RX_SDCAL1_ITER_TMR		0x004DU
>   #define RX_CDRLF_CNFG			0x0080U
> +#define RX_CDRLF_CNFG2			0x0081U
>   #define RX_CDRLF_CNFG3			0x0082U
>   #define RX_SIGDET_HL_FILT_TMR		0x0090U
>   #define RX_REE_GCSM1_CTRL		0x0108U
> @@ -204,6 +205,7 @@
>   #define RX_REE_GCSM1_EQENM_PH2		0x010AU
>   #define RX_REE_GCSM2_CTRL		0x0110U
>   #define RX_REE_PERGCSM_CTRL		0x0118U
> +#define RX_REE_PEAK_UTHR		0x0142U
>   #define RX_REE_ATTEN_THR		0x0149U
>   #define RX_REE_TAP1_CLIP		0x0171U
>   #define RX_REE_TAP2TON_CLIP		0x0172U
> @@ -212,6 +214,7 @@
>   #define RX_DIAG_DFE_CTRL		0x01E0U
>   #define RX_DIAG_DFE_AMP_TUNE_2		0x01E2U
>   #define RX_DIAG_DFE_AMP_TUNE_3		0x01E3U
> +#define RX_DIAG_REE_DAC_CTRL		0x01E4U
>   #define RX_DIAG_NQST_CTRL		0x01E5U
>   #define RX_DIAG_SIGDET_TUNE		0x01E8U
>   #define RX_DIAG_PI_RATE			0x01F4U
> @@ -3131,6 +3134,101 @@ static void cdns_torrent_phy_remove(struct platform_device *pdev)
>   	cdns_torrent_clk_cleanup(cdns_phy);
>   }
>   
> +/* Multi link PCIe configuration */
> +static struct cdns_reg_pairs ml_pcie_link_cmn_regs[] = {
> +	{0x0002, PHY_PLL_CFG},
> +	{0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0}
> +};

I think that some, if not all, of these new struct could be const, as 
elsewhere in this file.

> +
> +static struct cdns_reg_pairs ml_pcie_xcvr_diag_ln_regs[] = {
> +	{0x0100, XCVR_DIAG_HSCLK_SEL},
> +	{0x0001, XCVR_DIAG_HSCLK_DIV},
> +	{0x0812, XCVR_DIAG_PLLDRC_CTRL}
> +};

...

CJ