linux-kernel - Re: [PATCH v2 2/2] phy: cadence-torrent: Add PCIe multilink + USB with same SSC register config for 100 MHz refclk

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <24498c4e-c517-46b9-8d0c-ff1e3a308228@wanadoo.fr>
Date: Mon, 6 Jan 2025 23:05:35 +0100
From: Christophe JAILLET <christophe.jaillet@...adoo.fr>
To: Siddharth Vadapalli <s-vadapalli@...com>, vkoul@...nel.org,
 kishon@...nel.org, sjakhade@...ence.com, rogerq@...nel.org,
 thomas.richard@...tlin.com, u.kleine-koenig@...libre.com, eballetb@...hat.com
Cc: linux-phy@...ts.infradead.org, linux-kernel@...r.kernel.org,
 linux-arm-kernel@...ts.infradead.org, srk@...com
Subject: Re: [PATCH v2 2/2] phy: cadence-torrent: Add PCIe multilink + USB
 with same SSC register config for 100 MHz refclk

Le 06/01/2025 à 14:19, Siddharth Vadapalli a écrit :
> From: Swapnil Jakhade <sjakhade@...ence.com>
> 
> Add register sequences and support for PCIe multilink + USB configuration
> for 100MHz reference clock. The same SSC is used for both PCIe and USB.
> 
> Signed-off-by: Swapnil Jakhade <sjakhade@...ence.com>
> Co-developed-by: Siddharth Vadapalli <s-vadapalli@...com>
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@...com>
> ---
...

> @@ -2513,6 +2517,44 @@ int cdns_torrent_phy_configure_multilink(struct cdns_torrent_phy *cdns_phy)
>   
>   		phy_t1 = fns(cdns_phy->protocol_bitmask, 0);
>   		phy_t2 = fns(cdns_phy->protocol_bitmask, 1);
> +
> +		/**

Why kernel-doc like start of comment?
Only /* ?

> +		 * PCIe Multilink configuration can be supported along with a
> +		 * non-PCIe protocol. The existing limitation associated with
> +		 * the standalone PCIe Multilink configuration still remains,
> +		 * implying that there can be only two links (subnodes) of the
> +		 * PHY type PCIe which constitute the PCIe Multilink.
> +		 *
> +		 * Such configurations are handled by introducing a new protocol
> +		 * namely TYPE_PCIE_ML. Both of the PCIe links which have the
> +		 * protocol as TYPE_PCIE shall be treated as though the protocol
> +		 * corresponding to them is TYPE_PCIE_ML only for the sake of
> +		 * configuring the SERDES.
> +		 *
> +		 * PCIe Multilink configuration can be identified by checking if
> +		 * there are exactly two links with phy_type set to TYPE_PCIE.
> +		 * phy_t1 and phy_t2 are modified in such cases to support the
> +		 * PCIe Multilink configuration with a non-PCIe protocol.
> +		 */
...

> @@ -3134,6 +3180,37 @@ static void cdns_torrent_phy_remove(struct platform_device *pdev)
>   	cdns_torrent_clk_cleanup(cdns_phy);
>   }
>   
> +/* Multilink PCIe and USB Same SSC link configuration */
> +static struct cdns_reg_pairs ml_pcie_usb_link_cmn_regs[] = {
> +	{0x0002, PHY_PLL_CFG},
> +	{0x8600, CMN_PDIAG_PLL0_CLK_SEL_M0}
> +};

Maybe const could be added here and below?

> +
> +static struct cdns_reg_pairs ml_pcie_usb_xcvr_diag_ln_regs[] = {
> +	{0x0100, XCVR_DIAG_HSCLK_SEL},
> +	{0x0013, XCVR_DIAG_HSCLK_DIV},
> +	{0x0812, XCVR_DIAG_PLLDRC_CTRL}
> +};

...

CJ