linux-kernel - Re: (subset) [PATCH v8 0/5] Add CMN PLL clock controller driver for IPQ9574

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Message-ID: <173626793388.69400.11516262692578602679.b4-ty@kernel.org>
Date: Tue,  7 Jan 2025 10:38:46 -0600
From: Bjorn Andersson <andersson@...nel.org>
To: Michael Turquette <mturquette@...libre.com>,
	Stephen Boyd <sboyd@...nel.org>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Catalin Marinas <catalin.marinas@....com>,
	Will Deacon <will@...nel.org>,
	Konrad Dybcio <konradybcio@...nel.org>,
	Luo Jie <quic_luoj@...cinc.com>
Cc: linux-arm-msm@...r.kernel.org,
	linux-clk@...r.kernel.org,
	devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	linux-arm-kernel@...ts.infradead.org,
	quic_kkumarcs@...cinc.com,
	quic_suruchia@...cinc.com,
	quic_pavir@...cinc.com,
	quic_linchen@...cinc.com,
	quic_leiwei@...cinc.com,
	bartosz.golaszewski@...aro.org,
	srinivas.kandagatla@...aro.org,
	Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
	Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Subject: Re: (subset) [PATCH v8 0/5] Add CMN PLL clock controller driver for IPQ9574


On Fri, 03 Jan 2025 15:31:33 +0800, Luo Jie wrote:
> The CMN PLL clock controller in Qualcomm IPQ chipsets provides
> the clocks to the networking hardware blocks that are internal
> or external to the SoC, and to the GCC. This driver configures
> the CMN PLL clock controller to enable the output clocks. The
> networking blocks include the internal blocks such as PPE
> (Packet Process Engine) and PCS blocks, and external hardware
> such as Ethernet PHY or switch. The CMN PLL block also outputs
> fixed rate clocks to GCC, such as 24 MHZ as XO clock and 32 KHZ
> as sleep clock supplied to GCC.
> 
> [...]

Applied, thanks!

[2/5] clk: qcom: Add CMN PLL clock controller driver for IPQ SoC
      commit: f81715a4c87c3b75ca2640bb61b6c66506061a64

Best regards,
-- 
Bjorn Andersson <andersson@...nel.org>