linux-kernel - Re: [PATCH] media: tc358746: improve calculation of the D-PHY timing registers

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Message-ID: <20250107165238.vyuzjbzz6yn3cdxs@pengutronix.de>
Date: Tue, 7 Jan 2025 17:52:38 +0100
From: Marco Felsch <m.felsch@...gutronix.de>
To: Matthias Fend <matthias.fend@...end.at>
Cc: Mauro Carvalho Chehab <mchehab@...nel.org>, linux-media@...r.kernel.org,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH] media: tc358746: improve calculation of the D-PHY timing
 registers

On 25-01-07, Matthias Fend wrote:
> When calculating D-PHY registers, using data rates that are not multiples
> of 16 can lead to precision loss in division operations. This can result in
> register values that produce timing violations against the MIPI standard.
> 
> An example:
> cfg->hs_clk_rate = 294MHz
> hf_clk = 18
> 
> If the desired value in cfg->init is 100us, which is the minimum allowed
> value, then the LINEINITCNT register is calculated as 1799. But since the
> actual clock is 18.375MHz instead of 18MHz, this setting results in a time
> that is shorter than 100us and thus violates the standard. The correct
> value for LINEINITCNT would be 1837.
> 
> Improve the precision of calculations by using Hz instead of MHz as unit.
> 
> Signed-off-by: Matthias Fend <matthias.fend@...end.at>

Reviewed-by: Marco Felsch <m.felsch@...gutronix.de>