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Message-ID: <20250107105947.321847-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
Date: Tue, 7 Jan 2025 10:59:47 +0000
From: Prabhakar <prabhakar.csengg@...il.com>
To: Geert Uytterhoeven <geert+renesas@...der.be>,
Linus Walleij <linus.walleij@...aro.org>
Cc: linux-renesas-soc@...r.kernel.org,
linux-gpio@...r.kernel.org,
linux-kernel@...r.kernel.org,
Prabhakar <prabhakar.csengg@...il.com>,
Biju Das <biju.das.jz@...renesas.com>,
Fabrizio Castro <fabrizio.castro.jz@...esas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: [PATCH] pinctrl: renesas: rzg2l: Use configurable PFC mask
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Make the PFC mask for the PFC_mx register configurable to address
differences between SoCs in the RZ/G2L family and RZ/V2H.
On RZ/G2L family SoCs, the PFC_mx mask is `0x7` (3 bits), while on RZ/V2H
it is `0xf` (4 bits). The previous implementation hardcoded the PFC mask
as `0x7`, which caused incorrect behavior when configuring PFC registers
on RZ/V2H.
To resolve this, introduce a `pfcmask` field in the `rzg2l_hwcfg` structure
to make the mask value configurable based on the SoC. Update PFC-related
logic to use `hwcfg->pfcmask` instead of a hardcoded value. Additionally,
update hardware configuration definitions to include the appropriate mask
values (`0x7` for RZ/G2L family and `0xf` for RZ/V2H).
Fixes: 9bd95ac86e70 ("pinctrl: renesas: rzg2l: Add support for RZ/V2H SoC")
Reported-by: Hien Huynh <hien.huynh.px@...esas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 18 ++++++++++++------
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index ffcc5255724d..a36c73fd4159 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -159,7 +159,6 @@
#define PWPR_REGWE_B BIT(5) /* OEN Register Write Enable, known only in RZ/V2H(P) */
#define PM_MASK 0x03
-#define PFC_MASK 0x07
#define IEN_MASK 0x01
#define IOLH_MASK 0x03
#define SR_MASK 0x01
@@ -261,6 +260,7 @@ enum rzg2l_iolh_index {
* @func_base: base number for port function (see register PFC)
* @oen_max_pin: the maximum pin number supporting output enable
* @oen_max_port: the maximum port number supporting output enable
+ * @pfcmask: mask for the PFC_m register
*/
struct rzg2l_hwcfg {
const struct rzg2l_register_offsets regs;
@@ -273,6 +273,7 @@ struct rzg2l_hwcfg {
u8 func_base;
u8 oen_max_pin;
u8 oen_max_port;
+ u8 pfcmask;
};
struct rzg2l_dedicated_configs {
@@ -498,6 +499,7 @@ static void rzv2h_pmc_writeb(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset)
static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl,
u8 pin, u8 off, u8 func)
{
+ const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
unsigned long flags;
u32 reg;
@@ -505,7 +507,7 @@ static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl,
/* Set pin to 'Non-use (Hi-Z input protection)' */
reg = readw(pctrl->base + PM(off));
- reg &= ~(PM_MASK << (pin * 2));
+ reg &= ~(hwcfg->pfcmask << (pin * 2));
writew(reg, pctrl->base + PM(off));
pctrl->data->pwpr_pfc_lock_unlock(pctrl, false);
@@ -516,7 +518,7 @@ static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl,
/* Select Pin function mode with PFC register */
reg = readl(pctrl->base + PFC(off));
- reg &= ~(PFC_MASK << (pin * 4));
+ reg &= ~(hwcfg->pfcmask << (pin * 4));
writel(reg | (func << (pin * 4)), pctrl->base + PFC(off));
/* Switch to Peripheral pin function with PMC register */
@@ -3082,6 +3084,7 @@ static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, b
static void rzg2l_pinctrl_pm_setup_pfc(struct rzg2l_pinctrl *pctrl)
{
u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT;
+ const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
unsigned long flags;
spin_lock_irqsave(&pctrl->lock, flags);
@@ -3110,7 +3113,7 @@ static void rzg2l_pinctrl_pm_setup_pfc(struct rzg2l_pinctrl *pctrl)
continue;
/* Set pin to 'Non-use (Hi-Z input protection)' */
- pm &= ~(PM_MASK << (pin * 2));
+ pm &= ~(hwcfg->pfcmask << (pin * 2));
writew(pm, pctrl->base + PM(off));
/* Temporarily switch to GPIO mode with PMC register */
@@ -3118,8 +3121,8 @@ static void rzg2l_pinctrl_pm_setup_pfc(struct rzg2l_pinctrl *pctrl)
writeb(pmc, pctrl->base + PMC(off));
/* Select Pin function mode. */
- pfc &= ~(PFC_MASK << (pin * 4));
- pfc |= (cache->pfc[port] & (PFC_MASK << (pin * 4)));
+ pfc &= ~(hwcfg->pfcmask << (pin * 4));
+ pfc |= (cache->pfc[port] & (hwcfg->pfcmask << (pin * 4)));
writel(pfc, pctrl->base + PFC(off));
/* Switch to Peripheral pin function. */
@@ -3235,6 +3238,7 @@ static const struct rzg2l_hwcfg rzg2l_hwcfg = {
.iolh_groupb_oi = { 100, 66, 50, 33, },
.tint_start_index = 9,
.oen_max_pin = 0,
+ .pfcmask = 0x7,
};
static const struct rzg2l_hwcfg rzg3s_hwcfg = {
@@ -3268,6 +3272,7 @@ static const struct rzg2l_hwcfg rzg3s_hwcfg = {
.func_base = 1,
.oen_max_pin = 1, /* Pin 1 of P0 and P7 is the maximum OEN pin. */
.oen_max_port = 7, /* P7_1 is the maximum OEN port. */
+ .pfcmask = 0x7,
};
static const struct rzg2l_hwcfg rzv2h_hwcfg = {
@@ -3275,6 +3280,7 @@ static const struct rzg2l_hwcfg rzv2h_hwcfg = {
.pwpr = 0x3c04,
},
.tint_start_index = 17,
+ .pfcmask = 0xf,
};
static struct rzg2l_pinctrl_data r9a07g043_data = {
--
2.43.0
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