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Message-ID: <b198c395-5aa1-418a-82fb-936377c3caa2@amd.com>
Date: Wed, 8 Jan 2025 16:27:28 +0100
From: Michal Simek <michal.simek@....com>
To: Krzysztof Kozlowski <krzk@...nel.org>,
Shubhrajyoti Datta <shubhrajyoti.datta@....com>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Cc: git@....com
Subject: Re: [PATCH] dt-bindings: soc: Add new board description for Versal
NET
On 1/8/25 12:47, Krzysztof Kozlowski wrote:
> On 08/01/2025 12:33, Shubhrajyoti Datta wrote:
>> description: |
>> - Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC
>> + Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC or Versal Adaptive SoCs
>>
>> properties:
>> $nodename:
>> @@ -187,6 +187,10 @@ properties:
>> - const: qemu,mbv
>> - const: amd,mbv
>>
>> + - description: Xilinx Versal NET
>> + items:
>> + - const: xlnx,versal-net
>
> It is usually too difficult to use SoCs on their own. Just too small
> pins for our clumsy fingers. Therefore I don't get how this is supposed
> to be used...
>
> Anyway, provide the user for the binding (DTS).
ok. Let us strip our current DT from descriptions which are not upstreamed yet
and wire one board to be also listed.
Thanks,
Michal
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