lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <8ff20f2c-fe72-48a6-ad00-872ca20f5e8c@kernel.org>
Date: Wed, 8 Jan 2025 12:47:57 +0100
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Shubhrajyoti Datta <shubhrajyoti.datta@....com>,
 Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
 Conor Dooley <conor+dt@...nel.org>, Michal Simek <michal.simek@....com>,
 devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
 linux-kernel@...r.kernel.org
Cc: git@....com
Subject: Re: [PATCH] dt-bindings: soc: Add new board description for Versal
 NET

On 08/01/2025 12:33, Shubhrajyoti Datta wrote:
>  description: |
> -  Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC
> +  Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC or Versal Adaptive SoCs
>  
>  properties:
>    $nodename:
> @@ -187,6 +187,10 @@ properties:
>            - const: qemu,mbv
>            - const: amd,mbv
>  
> +      - description: Xilinx Versal NET
> +        items:
> +          - const: xlnx,versal-net

It is usually too difficult to use SoCs on their own. Just too small
pins for our clumsy fingers. Therefore I don't get how this is supposed
to be used...

Anyway, provide the user for the binding (DTS).

Best regards,
Krzysztof

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ