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Message-ID: <20250108113338.20289-1-shubhrajyoti.datta@amd.com>
Date: Wed, 8 Jan 2025 17:03:38 +0530
From: Shubhrajyoti Datta <shubhrajyoti.datta@....com>
To: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Michal Simek <michal.simek@....com>,
<devicetree@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>
CC: <git@....com>, Shubhrajyoti Datta <shubhrajyoti.datta@....com>
Subject: [PATCH] dt-bindings: soc: Add new board description for Versal NET
The Versal NET (Networked Adaptive Compute Acceleration Platform) from
AMD/Xilinx is a next-generation adaptive platform designed for high
performance computing, networking, and AI acceleration. It is part of the
Versal ACAP (Adaptive Compute Acceleration Platform) family.
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@....com>
---
Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
index 131aba5ed9f4..e0fa36be7e35 100644
--- a/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
+++ b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
@@ -10,7 +10,7 @@ maintainers:
- Michal Simek <michal.simek@....com>
description: |
- Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC
+ Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC or Versal Adaptive SoCs
properties:
$nodename:
@@ -187,6 +187,10 @@ properties:
- const: qemu,mbv
- const: amd,mbv
+ - description: Xilinx Versal NET
+ items:
+ - const: xlnx,versal-net
+
additionalProperties: true
...
--
2.17.1
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