linux-kernel - Re: [PATCH 2/2] arm64: dts: qcom: qcs615: add the GPU SMMU node

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Message-ID: <fgcpk3dxmhsqvjijzcben53f4gpihkc7fwyzafih4fgubbz7j6@qzpqjaudfnxi>
Date: Wed, 8 Jan 2025 16:34:53 -0600
From: Bjorn Andersson <andersson@...nel.org>
To: Qingqing Zhou <quic_qqzhou@...cinc.com>
Cc: konradybcio@...nel.org, robh@...nel.org, krzk+dt@...nel.org, 
	conor+dt@...nel.org, robimarko@...il.com, will@...nel.org, robin.murphy@....com, 
	joro@...tes.org, linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org, 
	linux-kernel@...r.kernel.org, iommu@...ts.linux.dev
Subject: Re: [PATCH 2/2] arm64: dts: qcom: qcs615: add the GPU SMMU node

On Fri, Nov 22, 2024 at 01:19:22PM +0530, Qingqing Zhou wrote:
> Add the Adreno GPU SMMU node for QCS615 platform.
> 

Please resubmit this in a series together with gpucc, gmu and gpu nodes.

Regards,
Bjorn

> Signed-off-by: Qingqing Zhou <quic_qqzhou@...cinc.com>
> ---
>  arch/arm64/boot/dts/qcom/qcs615.dtsi | 27 +++++++++++++++++++++++++++
>  1 file changed, 27 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> index 56af38d4f75f..4e0f26563db9 100644
> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> @@ -528,6 +528,33 @@
>  			#power-domain-cells = <1>;
>  		};
>  
> +		adreno_smmu: iommu@...0000 {
> +			compatible = "qcom,qcs615-smmu-500", "qcom,adreno-smmu",
> +				     "qcom,smmu-500", "arm,mmu-500";
> +			reg = <0x0 0x50a0000 0x0 0x10000>;
> +			#iommu-cells = <2>;
> +			#global-interrupts = <1>;
> +			dma-coherent;
> +
> +			power-domains = <&gpucc CX_GDSC>;
> +			clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
> +				 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
> +				 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
> +			clock-names = "mem",
> +				      "hlos",
> +				      "iface";
> +
> +			interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>;
> +		};
> +
>  		dc_noc: interconnect@...0000 {
>  			reg = <0x0 0x09160000 0x0 0x3200>;
>  			compatible = "qcom,qcs615-dc-noc";
> -- 
> 2.17.1
>