linux-kernel - Re: [PATCH v2 1/2] arm64: dts: qcom: qcs8300: add display dt nodes for MDSS, DPU, DisplayPort and eDP PHY

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Message-ID: <8cb5aa2d-54a7-4f41-b07c-b3c8256bf762@quicinc.com>
Date: Wed, 8 Jan 2025 16:21:04 +0800
From: Yongxing Mou <quic_yongmou@...cinc.com>
To: Konrad Dybcio <konrad.dybcio@....qualcomm.com>,
        Bjorn Andersson
	<andersson@...nel.org>,
        Konrad Dybcio <konradybcio@...nel.org>, Rob Herring
	<robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley
	<conor+dt@...nel.org>
CC: <linux-arm-msm@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2 1/2] arm64: dts: qcom: qcs8300: add display dt nodes
 for MDSS, DPU, DisplayPort and eDP PHY



On 2024/12/30 22:34, Konrad Dybcio wrote:
> On 26.12.2024 11:43 AM, Yongxing Mou wrote:
>> Add devicetree changes to enable MDSS display-subsystem,
>> display-controller(DPU), DisplayPort controller and eDP PHY for
>> Qualcomm QCS8300 platform.
>>
>> Signed-off-by: Yongxing Mou <quic_yongmou@...cinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/qcs8300.dtsi | 204 +++++++++++++++++++++++++++++++++-
>>   1 file changed, 203 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>> index 80226992a65d867124b33dfa490c3c9ca1030c75..8d88fe4a266432f05192d7ef0dd80362bdbdab85 100644
>> --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>> @@ -952,6 +952,206 @@ camcc: clock-controller@...0000 {
>>   			#power-domain-cells = <1>;
>>   		};
>>   
>> +		mdss: display-subsystem@...0000 {
>> +			compatible = "qcom,qcs8300-mdss";
>> +			reg = <0x0 0x0ae00000 0x0 0x1000>;
>> +			reg-names = "mdss";
>> +
>> +			interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY
>> +					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
>> +					<&mmss_noc MASTER_MDP1 QCOM_ICC_TAG_ACTIVE_ONLY
>> +					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
>> +					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
>> +					 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
>> +			interconnect-names = "mdp0-mem",
>> +					     "mdp1-mem",
>> +					     "cpu-cfg";
> 
> Only the CPU path should be ACTIVE_ONLY, the rest should be
> QCOM_ICC_TAG_ALWAYS
> 
Thank for point it. will update it in next patch.
>> +
>> +			resets = <&dispcc MDSS_DISP_CC_MDSS_CORE_BCR>;
>> +
>> +			power-domains = <&dispcc MDSS_DISP_CC_MDSS_CORE_GDSC>;
>> +
>> +			clocks = <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>,
>> +				 <&gcc GCC_DISP_HF_AXI_CLK>,
>> +				 <&dispcc MDSS_DISP_CC_MDSS_MDP_CLK>;
> 
> Please align the property order with x1e80100.dtsi
> 
Ok got it thanks. will update it as x1e80100.dtsi in next patch.
> [...]
> 
>> +			mdss_dp0_phy: phy@...2a00 {
>> +				compatible = "qcom,qcs8300-edp-phy", "qcom,sa8775p-edp-phy";
>> +
>> +				reg = <0x0 0x0aec2a00 0x0 0x19c>,
>> +				      <0x0 0x0aec2200 0x0 0xec>,
>> +				      <0x0 0x0aec2600 0x0 0xec>,
>> +				      <0x0 0x0aec2000 0x0 0x1c8>;
>> +
>> +				clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
>> +					 <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>;
>> +				clock-names = "aux",
>> +					      "cfg_ahb";
>> +
>> +				power-domains = <&rpmhpd RPMHPD_MMCX>;
> 
> The PHYs generally sit on a MX-like rail, please verify this
> 
We are currently verifying this power domain. We will validate it and 
update it accordingly. Thank you for pointing this out.
> Konrad