linux-kernel - [tip: x86/sev] x86/sev: Prevent GUEST_TSC_FREQ MSR interception for Secure TSC enabled guests

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Message-ID: <173641582648.399.3076847631804482712.tip-bot2@tip-bot2>
Date: Thu, 09 Jan 2025 09:43:46 -0000
From: "tip-bot2 for Nikunj A Dadhania" <tip-bot2@...utronix.de>
To: linux-tip-commits@...r.kernel.org
Cc: Nikunj A Dadhania <nikunj@....com>, "Borislav Petkov (AMD)" <bp@...en8.de>,
 Tom Lendacky <thomas.lendacky@....com>, x86@...nel.org,
 linux-kernel@...r.kernel.org
Subject: [tip: x86/sev] x86/sev: Prevent GUEST_TSC_FREQ MSR interception for
 Secure TSC enabled guests

The following commit has been merged into the x86/sev branch of tip:

Commit-ID:     38cc6495cdec18a448b9e1de45fedce4118833a2
Gitweb:        https://git.kernel.org/tip/38cc6495cdec18a448b9e1de45fedce4118833a2
Author:        Nikunj A Dadhania <nikunj@....com>
AuthorDate:    Mon, 06 Jan 2025 18:16:27 +05:30
Committer:     Borislav Petkov (AMD) <bp@...en8.de>
CommitterDate: Tue, 07 Jan 2025 21:26:19 +01:00

x86/sev: Prevent GUEST_TSC_FREQ MSR interception for Secure TSC enabled guests

The hypervisor should not be intercepting GUEST_TSC_FREQ MSR(0xcOO10134)
when Secure TSC is enabled. A #VC exception will be generated otherwise. If
this should occur and Secure TSC is enabled, terminate guest execution.

Signed-off-by: Nikunj A Dadhania <nikunj@....com>
Signed-off-by: Borislav Petkov (AMD) <bp@...en8.de>
Reviewed-by: Tom Lendacky <thomas.lendacky@....com>
Link: https://lore.kernel.org/r/20250106124633.1418972-8-nikunj@amd.com
---
 arch/x86/coco/sev/core.c         | 10 +++++++++-
 arch/x86/include/asm/msr-index.h |  1 +
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/arch/x86/coco/sev/core.c b/arch/x86/coco/sev/core.c
index cd5b9b7..106bded 100644
--- a/arch/x86/coco/sev/core.c
+++ b/arch/x86/coco/sev/core.c
@@ -1436,13 +1436,20 @@ static enum es_result __vc_handle_msr_caa(struct pt_regs *regs, bool write)
 /*
  * TSC related accesses should not exit to the hypervisor when a guest is
  * executing with Secure TSC enabled, so special handling is required for
- * accesses of MSR_IA32_TSC.
+ * accesses of MSR_IA32_TSC and MSR_AMD64_GUEST_TSC_FREQ.
  */
 static enum es_result __vc_handle_secure_tsc_msrs(struct pt_regs *regs, bool write)
 {
 	u64 tsc;
 
 	/*
+	 * GUEST_TSC_FREQ should not be intercepted when Secure TSC is enabled.
+	 * Terminate the SNP guest when the interception is enabled.
+	 */
+	if (regs->cx == MSR_AMD64_GUEST_TSC_FREQ)
+		return ES_VMM_ERROR;
+
+	/*
 	 * Writes: Writing to MSR_IA32_TSC can cause subsequent reads of the TSC
 	 *         to return undefined values, so ignore all writes.
 	 *
@@ -1474,6 +1481,7 @@ static enum es_result vc_handle_msr(struct ghcb *ghcb, struct es_em_ctxt *ctxt)
 	case MSR_SVSM_CAA:
 		return __vc_handle_msr_caa(regs, write);
 	case MSR_IA32_TSC:
+	case MSR_AMD64_GUEST_TSC_FREQ:
 		if (sev_status & MSR_AMD64_SNP_SECURE_TSC)
 			return __vc_handle_secure_tsc_msrs(regs, write);
 		else
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 3f3e2bc..9a71880 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -608,6 +608,7 @@
 #define MSR_AMD_PERF_CTL		0xc0010062
 #define MSR_AMD_PERF_STATUS		0xc0010063
 #define MSR_AMD_PSTATE_DEF_BASE		0xc0010064
+#define MSR_AMD64_GUEST_TSC_FREQ	0xc0010134
 #define MSR_AMD64_OSVW_ID_LENGTH	0xc0010140
 #define MSR_AMD64_OSVW_STATUS		0xc0010141
 #define MSR_AMD_PPIN_CTL		0xc00102f0