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Message-ID: <20250112150629.6999b500@jic23-huawei>
Date: Sun, 12 Jan 2025 15:06:29 +0000
From: Jonathan Cameron <jic23@...nel.org>
To: Angelo Dureghello <adureghello@...libre.com>
Cc: Lars-Peter Clausen <lars@...afoo.de>, Michael Hennerich
<Michael.Hennerich@...log.com>, David Lechner <dlechner@...libre.com>, Nuno
Sa <nuno.sa@...log.com>, Jonathan Cameron <Jonathan.Cameron@...wei.com>,
linux-iio@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3 8/9] iio: dac: ad3552r-hs: add ad3541/2r support
On Fri, 10 Jan 2025 11:24:20 +0100
Angelo Dureghello <adureghello@...libre.com> wrote:
> From: Angelo Dureghello <adureghello@...libre.com>
>
> A new FPGA HDL has been developed from ADI to support ad354xr
> devices.
>
> Add support for ad3541r and ad3542r with following additions:
>
> - use common device_info structures for hs and non hs drivers,
> - DMA buffering, use DSPI mode for ad354xr and QSPI for ad355xr,
> - change sample rate to respect number of lanes.
>
> Signed-off-by: Angelo Dureghello <adureghello@...libre.com>
I think the question I posted on v2 (missing there was a v3)
still applies. Please check that thread.
Jonathan
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