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Message-ID: <CAEEQ3w=fgb7Jxg6SP_hp0Z+T0Tfb-_Pa4-CzU8PpGUKA+dHxyA@mail.gmail.com>
Date: Mon, 13 Jan 2025 19:29:39 +0800
From: yunhui cui <cuiyunhui@...edance.com>
To: Andrew Jones <ajones@...tanamicro.com>
Cc: alexghiti@...osinc.com, andybnac@...il.com, aou@...s.berkeley.edu,
charlie@...osinc.com, cleger@...osinc.com, conor.dooley@...rochip.com,
conor@...nel.org, corbet@....net, evan@...osinc.com, jesse@...osinc.com,
linux-doc@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-kselftest@...r.kernel.org, linux-riscv@...ts.infradead.org,
palmer@...belt.com, paul.walmsley@...ive.com, samuel.holland@...ive.com,
shuah@...nel.org
Subject: Re: [External] Re: [PATCH v3 2/3] RISC-V: hwprobe: Expose Zicbom
extension and its block size
Hi drew,
On Mon, Jan 13, 2025 at 5:07 PM Andrew Jones <ajones@...tanamicro.com> wrote:
>
> On Mon, Jan 13, 2025 at 04:36:34PM +0800, Yunhui Cui wrote:
> > Expose Zicbom through hwprobe and also provide a key to extract its
> > respective block size.
> >
> > Signed-off-by: Yunhui Cui <cuiyunhui@...edance.com>
> > ---
> > Documentation/arch/riscv/hwprobe.rst | 6 ++++++
> > arch/riscv/include/asm/hwprobe.h | 2 +-
> > arch/riscv/include/uapi/asm/hwprobe.h | 2 ++
> > arch/riscv/kernel/sys_hwprobe.c | 6 ++++++
> > 4 files changed, 15 insertions(+), 1 deletion(-)
> >
> > diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
> > index 955fbcd19ce9..7a47cbdbcf8e 100644
> > --- a/Documentation/arch/riscv/hwprobe.rst
> > +++ b/Documentation/arch/riscv/hwprobe.rst
> > @@ -94,6 +94,9 @@ The following keys are defined:
> > * :c:macro:`RISCV_HWPROBE_EXT_ZICBOZ`: The Zicboz extension is supported, as
> > ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
> >
> > + * :c:macro:`RISCV_HWPROBE_EXT_ZICBOM`: The Zicbom extension is supported, as
> > + ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
> > +
>
> This should come after RISCV_HWPROBE_EXT_SUPM since this document has the
> defines sorted in the order in which they are introduced (although I
> personally wouldn't mind if we ordered them alphabetically instead)
OK
>
> > * :c:macro:`RISCV_HWPROBE_EXT_ZBC` The Zbc extension is supported, as defined
> > in version 1.0 of the Bit-Manipulation ISA extensions.
> >
> > @@ -273,6 +276,9 @@ The following keys are defined:
> > * :c:macro:`RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE`: An unsigned int which
> > represents the size of the Zicboz block in bytes.
> >
> > +* :c:macro:`RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE`: An unsigned int which
> > + represents the size of the Zicbom block in bytes.
> > +
>
> Should be moved below RISCV_HWPROBE_KEY_TIME_CSR_FREQ
Why should it be moved below RISCV_HWPROBE_KEY_TIME_CSR_FREQ?
> > * :c:macro:`RISCV_HWPROBE_KEY_HIGHEST_VIRT_ADDRESS`: An unsigned long which
> > represent the highest userspace virtual address usable.
> >
> > diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h
> > index 1ce1df6d0ff3..89379f9a2e6e 100644
> > --- a/arch/riscv/include/asm/hwprobe.h
> > +++ b/arch/riscv/include/asm/hwprobe.h
> > @@ -8,7 +8,7 @@
> >
> > #include <uapi/asm/hwprobe.h>
> >
> > -#define RISCV_HWPROBE_MAX_KEY 10
> > +#define RISCV_HWPROBE_MAX_KEY 11
> >
> > static inline bool riscv_hwprobe_key_is_valid(__s64 key)
> > {
> > diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
> > index 3af142b99f77..892dd71a3793 100644
> > --- a/arch/riscv/include/uapi/asm/hwprobe.h
> > +++ b/arch/riscv/include/uapi/asm/hwprobe.h
> > @@ -73,6 +73,7 @@ struct riscv_hwprobe {
> > #define RISCV_HWPROBE_EXT_ZCMOP (1ULL << 47)
> > #define RISCV_HWPROBE_EXT_ZAWRS (1ULL << 48)
> > #define RISCV_HWPROBE_EXT_SUPM (1ULL << 49)
> > +#define RISCV_HWPROBE_EXT_ZICBOM (1ULL << 50)
> > #define RISCV_HWPROBE_KEY_CPUPERF_0 5
> > #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
> > #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)
> > @@ -90,6 +91,7 @@ struct riscv_hwprobe {
> > #define RISCV_HWPROBE_MISALIGNED_SCALAR_FAST 3
> > #define RISCV_HWPROBE_MISALIGNED_SCALAR_UNSUPPORTED 4
> > #define RISCV_HWPROBE_KEY_MISALIGNED_VECTOR_PERF 10
> > +#define RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE 11
>
> Move below the bit defines of RISCV_HWPROBE_KEY_MISALIGNED_VECTOR_PERF
> (notice how its bit defines are indented, indicating they belong to it)
OK
>
> > #define RISCV_HWPROBE_MISALIGNED_VECTOR_UNKNOWN 0
> > #define RISCV_HWPROBE_MISALIGNED_VECTOR_SLOW 2
> > #define RISCV_HWPROBE_MISALIGNED_VECTOR_FAST 3
> > diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
> > index cb93adfffc48..affcc3e58df9 100644
> > --- a/arch/riscv/kernel/sys_hwprobe.c
> > +++ b/arch/riscv/kernel/sys_hwprobe.c
> > @@ -107,6 +107,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
> > EXT_KEY(ZCB);
> > EXT_KEY(ZCMOP);
> > EXT_KEY(ZICBOZ);
> > + EXT_KEY(ZICBOM);
>
> This list is in alphabetical order, which means ZICBOM should come before
> ZICBOZ.
OK
>
> > EXT_KEY(ZICOND);
> > EXT_KEY(ZIHINTNTL);
> > EXT_KEY(ZIHINTPAUSE);
> > @@ -278,6 +279,11 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair,
> > if (hwprobe_ext0_has(cpus, RISCV_HWPROBE_EXT_ZICBOZ))
> > pair->value = riscv_cboz_block_size;
> > break;
> > + case RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE:
> > + pair->value = 0;
> > + if (hwprobe_ext0_has(cpus, RISCV_HWPROBE_EXT_ZICBOM))
> > + pair->value = riscv_cbom_block_size;
> > + break;
> > case RISCV_HWPROBE_KEY_HIGHEST_VIRT_ADDRESS:
> > pair->value = user_max_virt_addr();
> > break;
> > --
> > 2.39.2
> >
>
> Thanks,
> drew
Thanks,
Yunhui
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