linux-kernel - Re: [REGRESSION] mipsel: no RTC CMOS on the Malta platform in QEMU

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-Id: <08fe1ebb-b9c4-46c7-a6ab-5a336ec3b771@app.fastmail.com>
Date: Tue, 14 Jan 2025 10:59:33 +0100
From: "Arnd Bergmann" <arnd@...db.de>
To: "Geert Uytterhoeven" <geert@...ux-m68k.org>,
 "Jiaxun Yang" <jiaxun.yang@...goat.com>
Cc: Mateusz Jończyk <mat.jonczyk@...pl>,
 "linux-mips@...r.kernel.org" <linux-mips@...r.kernel.org>,
 Linux-Arch <linux-arch@...r.kernel.org>, linux-kernel@...r.kernel.org,
 "Baoquan He" <bhe@...hat.com>,
 "Thomas Bogendoerfer" <tsbogend@...ha.franken.de>,
 "Alexandre Belloni" <alexandre.belloni@...tlin.com>,
 regressions@...ts.linux.dev
Subject: Re: [REGRESSION] mipsel: no RTC CMOS on the Malta platform in QEMU

On Tue, Jan 14, 2025, at 09:02, Geert Uytterhoeven wrote:
> On Tue, Jan 14, 2025 at 12:32 AM Jiaxun Yang <jiaxun.yang@...goat.com> wrote:
>> 在2025年1月13日一月 下午10:16，Mateusz Jończyk写道：

>> > #ifndef PCI_IOBASE
>> > #define PCI_IOBASE ((void __iomem *)0)
>> > #endif
>> >
>> > That PCI_IOBASE value above is AFAIK incorrect for MIPS (it should be
>> > defined to mips_io_port_base as far as I can tell), but this does not
>> > matter much here.
>>
>> You are right, this is what should be done.
>>
>> A quick fix would be #undef PCI_IOBASE in arch/mips/include/asm/io.h
>> just after including #include <asm-generic/io.h>, with ralink and loongson64
>> as exception.
>
> Shouldn't arch/mips/include/asm/io.h do
>
>     #define PCI_IOBASE mips_io_port_base
>
> unconditionally, _before_ including  <asm-generic/io.h>?

Yes, I think this would make the most sense, but the ordering
with the PCI initialization needs to be done carefully,
to ensure that PCI_IOBASE has its final value before the first
call to pci_remap_iospace().

>> In the long term, we should scrutinize platform usage of mips_io_base
>> following ralink's approach.
>
> Currently ralink handles that in a mach-specific include:
>
>     arch/mips/include/asm/mach-ralink/spaces.h:#define PCI_IOBASE
> mips_io_port_base
>
> Loongson does it differently:
>
>     arch/mips/include/asm/mach-loongson64/spaces.h:#define PCI_IOBASE
>      _AC(0xc000000000000000 + SZ_128K, UL)
>
> But still sets mips_io_port_base in prom_init():
>
>     arch/mips/loongson64/init.c:    set_io_port_base(PCI_IOBASE);
>
> so defining PCI_IOBASE to mips_io_port_base in the main <asm/io.h>
> should work.

This probably requires calling set_io_port_base() with the
actual virtual address rather than self-assigning the
uninitialized mips_io_port_base.

I assume the reason for loongson64 being different from every
other mips platform is the same as why it calls into the
logic_pio_register_range() directly. I don't understand that
code, but it's probably because it has ISA/LPC devices that
are directly wired to a non-memory-mapped set of registers
instead of them being behind a PCI bridge like the other
platforms. The idea of logic_pio is to have a more generic
way to redirect arbitrary port ranges into bus specific
function calls, where normal PCI (on non-x86) assumes that
all I/O ports are mapped into a small contiguous ranges
of virtual addresses.

   Arnd