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Message-ID: <a81ca6f2-2f09-4836-b614-b169d5c65bfb@quicinc.com>
Date: Wed, 15 Jan 2025 14:47:52 -0800
From: Melody Olvera <quic_molvera@...cinc.com>
To: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
CC: Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio
<konradybcio@...nel.org>,
Conor Dooley <conor@...nel.org>, Rob Herring
<robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley
<conor+dt@...nel.org>,
Satya Durga Srinivasu Prabhala
<quic_satyap@...cinc.com>,
Trilok Soni <quic_tsoni@...cinc.com>, <linux-arm-msm@...r.kernel.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 4/4] arm64: dts: qcom: sm8750: Add LLCC node
On 1/14/2025 2:59 AM, Dmitry Baryshkov wrote:
> On Mon, Jan 13, 2025 at 01:26:43PM -0800, Melody Olvera wrote:
>> Add LLCC node for SM8750 SoC.
>>
>> Signed-off-by: Melody Olvera <quic_molvera@...cinc.com>
>> ---
>> arch/arm64/boot/dts/qcom/sm8750.dtsi | 11 +++++++++++
>> 1 file changed, 11 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
>> index 3bbd7d18598ee0a3a0d5130c03a3166e1fc14d82..3cd7b40bdde68ac00c3dbe7fb3f20ebb2ba27045 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
>> @@ -2888,6 +2888,17 @@ gem_noc: interconnect@...00000 {
>> #interconnect-cells = <2>;
>> };
>>
>> + cache-controller@...00000 {
>> + compatible = "qcom,sm8750-llcc";
>> + reg = <0x0 0x24800000 0x0 0x200000>, <0x0 0x25800000 0x0 0x200000>,
>> + <0x0 0x24C00000 0x0 0x200000>, <0x0 0x25C00000 0x0 0x200000>,
>> + <0x0 0x26800000 0x0 0x200000>, <0x0 0x26C00000 0x0 0x200000>;
>> + reg-names = "llcc0_base", "llcc1_base",
>> + "llcc2_base", "llcc3_base",
>> + "llcc_broadcast_base", "llcc_broadcast_and_base";
>> + interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
>> + };
> PLease take a look at sm8650 and change your patch accordingly.
>
> NAK
Apologies; the contents of this patch are very similar to sm8650, just
different offsets.
Only major diffs I see here are the node namde (cache-controller vs
system-cache-controller)
and the formatting (two regs/line vs one reg/line). Is there anything
else you mean by
this comment that I'm missing?
Thanks,
Melody
>
>> +
>> nsp_noc: interconnect@...c0000 {
>> compatible = "qcom,sm8750-nsp-noc";
>> reg = <0x0 0x320c0000 0x0 0x13080>;
>>
>> --
>> 2.46.1
>>
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