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Message-ID: <8d455825-8c7c-4f92-8485-280275d4da32@quicinc.com>
Date: Wed, 15 Jan 2025 14:49:07 -0800
From: Melody Olvera <quic_molvera@...cinc.com>
To: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
CC: Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio
<konradybcio@...nel.org>,
Conor Dooley <conor@...nel.org>, Rob Herring
<robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley
<conor+dt@...nel.org>,
Satya Durga Srinivasu Prabhala
<quic_satyap@...cinc.com>,
Trilok Soni <quic_tsoni@...cinc.com>, <linux-arm-msm@...r.kernel.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 3/4] soc: qcom: llcc-qcom: Add support for SM8750
On 1/14/2025 2:54 AM, Dmitry Baryshkov wrote:
> On Mon, Jan 13, 2025 at 01:26:42PM -0800, Melody Olvera wrote:
>> Add system cache table and configs for SM8750 SoCs.
>>
>> Signed-off-by: Melody Olvera <quic_molvera@...cinc.com>
>> ---
>> drivers/soc/qcom/llcc-qcom.c | 51 ++++++++++++++++++++++++++++++++++++++++++++
>> 1 file changed, 51 insertions(+)
>>
>> diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
>> index 4379b5baa011aa850a2b65ec20b32519d9331be4..f4cb158e0cf9eb82147ee461f98d0e928e5759a0 100644
>> --- a/drivers/soc/qcom/llcc-qcom.c
>> +++ b/drivers/soc/qcom/llcc-qcom.c
>> @@ -2770,6 +2770,41 @@ static const struct llcc_slice_config qcs8300_data[] = {
>> },
>> };
>>
>> +static const struct llcc_slice_config sm8750_data[] = {
>> + {LLCC_CPUSS, 1, 5120, 1, 0, 0xFFFFFFFF, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
> NAK, things have changed in the driver.
Oh yes I see now. Apologies; will fix in next ps.
Thanks,
Melody
>
>> + {LLCC_MDMHPFX, 24, 1024, 5, 1, 0xFFFFFFFF, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
>> + {LLCC_VIDSC0, 2, 512, 4, 1, 0xFFFFFFFF, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
>> + {LLCC_AUDIO, 35, 512, 1, 1, 0xFFFFFFFF, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
>> + {LLCC_MDMHPGRW, 25, 1024, 5, 0, 0xFFFFFFFF, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
>> + {LLCC_MODHW, 26, 1024, 1, 1, 0xFFFFFFFF, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
>> + {LLCC_CMPT, 34, 4096, 1, 1, 0xFFFFFFFF, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
>> + {LLCC_GPUHTW, 11, 512, 1, 1, 0xFFFFFFFF, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
>> + {LLCC_GPU, 9, 5632, 1, 1, 0xFFFFFFFF, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0},
>> + {LLCC_MMUHWT, 18, 768, 1, 1, 0xFFFFFFFF, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
>> + {LLCC_DISP, 16, 7168, 1, 1, 0xFFFFFFFF, 0, 2, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0},
>> + {LLCC_VIDFW, 17, 0, 4, 1, 0xFFFFFFFF, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
>> + {LLCC_CAMFW, 20, 0, 4, 1, 0xFFFFFFFF, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
>> + {LLCC_MDMPNG, 27, 256, 5, 1, 0xF0000000, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
>> + {LLCC_AUDHW, 22, 512, 1, 1, 0xFFFFFFFF, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
>> + {LLCC_CVP, 8, 800, 5, 1, 0xFFFFFFFF, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0},
>> + {LLCC_MODPE, 29, 256, 1, 1, 0xF0000000, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0},
>> + {LLCC_WRCACHE, 31, 512, 1, 1, 0xFFFFFFFF, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
>> + {LLCC_CVPFW, 19, 64, 4, 1, 0xFFFFFFFF, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
>> + {LLCC_CMPTHCP, 15, 256, 4, 1, 0xFFFFFFFF, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
>> + {LLCC_LCPDARE, 30, 128, 5, 1, 0xFFFFFFFF, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0},
>> + {LLCC_AENPU, 3, 3072, 1, 1, 0xFFFFFFFF, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
>> + {LLCC_ISLAND1, 12, 7936, 7, 1, 0, 0x7FFFFFFF, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
>> + {LLCC_DISP_WB, 23, 512, 4, 1, 0xFFFFFFFF, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
>> + {LLCC_VIDVSP, 4, 256, 4, 1, 0xFFFFFFFF, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
>> + {LLCC_VIDDEC, 5, 6144, 4, 1, 0xFFFFFFFF, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0},
>> + {LLCC_CAMOFE, 33, 6144, 4, 1, 0xFFFFFFFF, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0},
>> + {LLCC_CAMRTIP, 13, 1024, 4, 1, 0xFFFFFFFF, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0},
>> + {LLCC_CAMSRTIP, 14, 6144, 4, 1, 0xFFFFFFFF, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0},
>> + {LLCC_CAMRTRF, 7, 3584, 3, 1, 0xFFFFFFFF, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0},
>> + {LLCC_CAMSRTRF, 21, 6144, 1, 1, 0xFFFFFFFF, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0},
>> + {LLCC_CPUSSMPAM, 6, 2048, 1, 1, 0xFFFFFFFF, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
>> +};
>> +
>> static const struct llcc_slice_config qdu1000_data_2ch[] = {
>> {
>> .usecase_id = LLCC_MDMHPGRW,
>> @@ -3432,6 +3467,16 @@ static const struct qcom_llcc_config sm8650_cfg[] = {
>> },
>> };
>>
>> +static const struct qcom_llcc_config sm8750_cfg[] = {
>> + {
>> + .sct_data = sm8750_data,
>> + .size = ARRAY_SIZE(sm8750_data),
>> + .skip_llcc_cfg = false,
>> + .reg_offset = llcc_v6_reg_offset,
>> + .edac_reg_offset = &llcc_v6_edac_reg_offset,
>> + },
>> +};
>> +
>> static const struct qcom_llcc_config x1e80100_cfg[] = {
>> {
>> .sct_data = x1e80100_data,
>> @@ -3542,6 +3587,11 @@ static const struct qcom_sct_config sm8650_cfgs = {
>> .num_config = ARRAY_SIZE(sm8650_cfg),
>> };
>>
>> +static const struct qcom_sct_config sm8750_cfgs = {
>> + .llcc_config = sm8750_cfg,
>> + .num_config = ARRAY_SIZE(sm8750_cfg),
>> +};
>> +
>> static const struct qcom_sct_config x1e80100_cfgs = {
>> .llcc_config = x1e80100_cfg,
>> .num_config = ARRAY_SIZE(x1e80100_cfg),
>> @@ -4306,6 +4356,7 @@ static const struct of_device_id qcom_llcc_of_match[] = {
>> { .compatible = "qcom,sm8450-llcc", .data = &sm8450_cfgs },
>> { .compatible = "qcom,sm8550-llcc", .data = &sm8550_cfgs },
>> { .compatible = "qcom,sm8650-llcc", .data = &sm8650_cfgs },
>> + { .compatible = "qcom,sm8750-llcc", .data = &sm8750_cfgs },
>> { .compatible = "qcom,x1e80100-llcc", .data = &x1e80100_cfgs },
>> { }
>> };
>>
>> --
>> 2.46.1
>>
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