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Message-ID: <6e35eea5-2c7b-5d71-f39d-f9196a3c1b76@quicinc.com>
Date: Fri, 24 Jan 2025 13:56:25 +0530
From: Krishna Chaitanya Chundru <quic_krichai@...cinc.com>
To: Manivannan Sadhasivam <mani@...nel.org>,
Krishna Chaitanya Chundru
<krishna.chundru@....qualcomm.com>
CC: <cros-qcom-dts-watchers@...omium.org>,
Bjorn Andersson
<andersson@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>, Rob Herring
<robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley
<conor+dt@...nel.org>,
Lorenzo Pieralisi <lpieralisi@...nel.org>,
Krzysztof WilczyĆski <kw@...ux.com>,
Manivannan Sadhasivam
<manivannan.sadhasivam@...aro.org>,
Bjorn Helgaas <bhelgaas@...gle.com>, Jingoo Han <jingoohan1@...il.com>,
<linux-arm-msm@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <linux-pci@...r.kernel.org>,
<quic_vbadigan@...cinc.com>, <quic_vpernami@...cinc.com>,
<quic_mrana@...cinc.com>, <mmareddy@...cinc.com>
Subject: Re: [PATCH v3 3/4] PCI: dwc: Reduce DT reads by allocating host
bridge via DWC glue driver
On 1/24/2025 11:48 AM, Manivannan Sadhasivam wrote:
> On Tue, Jan 21, 2025 at 02:32:21PM +0530, Krishna Chaitanya Chundru wrote:
>> Allow DWC glue drivers to allocate the host bridge, avoiding redundant
>> device tree reads primarily in dw_pcie_ecam_supported().
>>
>
> I don't understand what you mean by 'redundant device tree reads'. Please
> explain.
>
In dw_pcie_ecam_supported () we are trying to read bus-range to find
maximum bus range value. devm_pci_alloc_host_bridge() is already reading
bus range it. If we move devm_pci_alloc_host_bridge() to start of the
controller probe we can avoid reading the dt and use values stored in
the host bridge.
This was recommended by bjorn in the v2.
I will update the commit text in the next series.
> - Mani
>
>> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@....qualcomm.com>
>> ---
>> drivers/pci/controller/dwc/pcie-designware-host.c | 13 +++++++------
>> 1 file changed, 7 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
>> index 3888f9fe5af1..0acf9db44f2c 100644
>> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
>> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
>> @@ -484,8 +484,8 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp)
>> struct device *dev = pci->dev;
>> struct device_node *np = dev->of_node;
>> struct platform_device *pdev = to_platform_device(dev);
>> + struct pci_host_bridge *bridge = pp->bridge;
>> struct resource_entry *win;
>> - struct pci_host_bridge *bridge;
>> struct resource *res;
>> int ret;
>>
>> @@ -497,11 +497,12 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp)
>> return -ENODEV;
>> }
>>
>> - bridge = devm_pci_alloc_host_bridge(dev, 0);
>> - if (!bridge)
>> - return -ENOMEM;
>> -
>> - pp->bridge = bridge;
>> + if (!pp->bridge) {
>> + bridge = devm_pci_alloc_host_bridge(dev, 0);
>> + if (!bridge)
>> + return -ENOMEM;
>> + pp->bridge = bridge;
>> + }
>>
>> pp->cfg0_size = resource_size(res);
>> pp->cfg0_base = res->start;
>>
>> --
>> 2.34.1
>>
>
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