linux-kernel - Re: [PATCH 3/6] phy: qcom: qmp-pcie: Add X1P42100 Gen4x4 PHY

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Message-ID: <20250126163222.nhcxvr4m2vncwi23@thinkpad>
Date: Sun, 26 Jan 2025 22:02:22 +0530
From: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
To: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
Cc: Konrad Dybcio <konradybcio@...nel.org>, Vinod Koul <vkoul@...nel.org>,
	Kishon Vijay Abraham I <kishon@...nel.org>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Bjorn Andersson <andersson@...nel.org>,
	Marijn Suijten <marijn.suijten@...ainline.org>,
	linux-arm-msm@...r.kernel.org, linux-phy@...ts.infradead.org,
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
	Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Subject: Re: [PATCH 3/6] phy: qcom: qmp-pcie: Add X1P42100 Gen4x4 PHY

On Sun, Jan 26, 2025 at 01:39:05PM +0200, Dmitry Baryshkov wrote:
> On Sun, Jan 26, 2025 at 12:59:52PM +0530, Manivannan Sadhasivam wrote:
> > 
> > 
> > On January 25, 2025 11:00:23 PM GMT+05:30, Dmitry Baryshkov <dmitry.baryshkov@...aro.org> wrote:
> > >On Sat, Jan 25, 2025 at 04:31:19AM +0100, Konrad Dybcio wrote:
> > >> From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
> > >> 
> > >> Add a new, common configuration for Gen4x4 V6 PHYs without an init
> > >> sequence.
> > >> 
> > >> The bootloader configures the hardware once and the OS retains that
> > >> configuration by using the NOCSR reset line (which doesn't drop
> > >> register state on assert) in place of the "full reset" one.
> > >
> > >I know your opinion, but my 2c would still be for not depending on the
> > >bootloader. I think that was the rule for ages for many possible
> > >reasons.
> > >
> > 
> > But if Linux or other OS can trust the bootloader, then it makes perfect sense to rely on them. Obviously, the question here is that on which platforms this level of trust should be established. And the answer I got was starting from the compute platforms (atleast X1E).
> 
> Is there any way how those values can be lost that we still might want
> to support ? The GDSC going to the OFF state? Some deep sleep state or a
> power collapse? Actual suspend to RAM (instead of current S2Idle)?
> 

As per Konrad's reply to my identical question, PHY register state is supposed
to be maintained by MX domain even during CX PC. This seem to be case on X1E
based platforms (compute).

> > 
> > So let's take it on an experimental basis and see how it goes? If at all any problem arises, we can always resort to in kernel sequences.
> 
> Sounds like a good proposal. Can possibly have a corresponding 'do not
> merge' patch with actual init tables?
> 

I don't find it really required. If the init sequences are really needed, we
know where to find them.

- Mani

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