linux-kernel - Re: [PATCH v5 4/5] arm64: dts: agilex: add dts enabling PCIe Root Port

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Message-ID: <58f7925c-dbed-4a5e-8e7d-095bef197931@kernel.org>
Date: Wed, 29 Jan 2025 10:49:15 +0100
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Matthew Gerlach <matthew.gerlach@...ux.intel.com>, lpieralisi@...nel.org,
 kw@...ux.com, manivannan.sadhasivam@...aro.org, robh@...nel.org,
 bhelgaas@...gle.com, krzk+dt@...nel.org, conor+dt@...nel.org,
 dinguyen@...nel.org, joyce.ooi@...el.com, linux-pci@...r.kernel.org,
 devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Cc: matthew.gerlach@...era.com, peter.colberg@...era.com
Subject: Re: [PATCH v5 4/5] arm64: dts: agilex: add dts enabling PCIe Root
 Port

On 27/01/2025 18:35, Matthew Gerlach wrote:
> Add a device tree enabling PCIe Root Port support on
> an Agilex F-series Development Kit which has the
> P-tile variant PCIe IP.

Please wrap commit message according to Linux coding style / submission
process (neither too early nor over the limit):
https://elixir.bootlin.com/linux/v6.4-rc1/source/Documentation/process/submitting-patches.rst#L597

> 
> Signed-off-by: Matthew Gerlach <matthew.gerlach@...ux.intel.com>
> ---
> v3:
>  - Remove accepted patches from patch set.
> ---
>  arch/arm64/boot/dts/intel/Makefile               |  1 +
>  .../socfpga_agilex7f_socdk_pcie_root_port.dts    | 16 ++++++++++++++++
>  2 files changed, 17 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex7f_socdk_pcie_root_port.dts
> 
> diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile
> index d39cfb723f5b..737e81c3c3f7 100644
> --- a/arch/arm64/boot/dts/intel/Makefile
> +++ b/arch/arm64/boot/dts/intel/Makefile
> @@ -2,6 +2,7 @@
>  dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \
>  				socfpga_agilex_socdk.dtb \
>  				socfpga_agilex_socdk_nand.dtb \
> +				socfpga_agilex7f_socdk_pcie_root_port.dtb \
>  				socfpga_agilex5_socdk.dtb \
>  				socfpga_n5x_socdk.dtb
>  dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb
> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex7f_socdk_pcie_root_port.dts b/arch/arm64/boot/dts/intel/socfpga_agilex7f_socdk_pcie_root_port.dts
> new file mode 100644
> index 000000000000..76a989ba6a44
> --- /dev/null
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex7f_socdk_pcie_root_port.dts
> @@ -0,0 +1,16 @@
> +// SPDX-License-Identifier:     GPL-2.0
> +/*
> + * Copyright (C) 2024, Intel Corporation
> + */
> +
> +#include "socfpga_agilex_socdk.dts"
> +#include "socfpga_agilex_pcie_root_port.dtsi"
> +

Missing board compatible, missing bindings.

> +&pcie_0_pcie_aglx {
> +	status = "okay";
> +	compatible = "altr,pcie-root-port-3.0-p-tile";

Why do you define the compatible here, not in DTSI? This is highly
unusual and confusing. Also, compatible is never the last property, but
opposite.

Plus:

Please run scripts/checkpatch.pl and fix reported warnings. After that,
run also `scripts/checkpatch.pl --strict` and (probably) fix more
warnings. Some warnings can be ignored, especially from --strict run,
but the code here looks like it needs a fix. Feel free to get in touch
if the warning is not clear.

It does not look like you tested the DTS against bindings. Please run
`make dtbs_check W=1` (see
Documentation/devicetree/bindings/writing-schema.rst or
https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/
for instructions).
Maybe you need to update your dtschema and yamllint. Don't rely on
distro packages for dtschema and be sure you are using the latest
released dtschema.



Best regards,
Krzysztof