linux-kernel - Re: [PATCH RFC] drm/msm/dsi/phy: Program clock inverters in correct register

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Message-ID: <4a27c3f2-6b36-42bf-b323-2cfb0014ca58@linaro.org>
Date: Wed, 29 Jan 2025 15:49:55 +0100
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
Cc: Rob Clark <robdclark@...il.com>, Abhinav Kumar
 <quic_abhinavk@...cinc.com>, Sean Paul <sean@...rly.run>,
 Marijn Suijten <marijn.suijten@...ainline.org>,
 David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>,
 linux-arm-msm@...r.kernel.org, dri-devel@...ts.freedesktop.org,
 freedreno@...ts.freedesktop.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH RFC] drm/msm/dsi/phy: Program clock inverters in correct
 register

On 29/01/2025 15:31, Dmitry Baryshkov wrote:
> On Wed, Jan 29, 2025 at 12:55:04PM +0100, Krzysztof Kozlowski wrote:
>> Since SM8250 all downstream sources program clock inverters in
>> PLL_CLOCK_INVERTERS_1 register and leave the PLL_CLOCK_INVERTERS as
>> reset value (0x0).  The most recent Hardware Programming Guide for 3 nm,
>> 4 nm, 5 nm and 7 nm PHYs also mention PLL_CLOCK_INVERTERS_1.
>>
>> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
>>
>> ---
>>
>> Not tested except my work-in-progress oon SM8750. Not sure what is the
>> impact, so also no Fixes tag.
> 
> I'd say,
> 
> Fixes: 1ef7c99d145c ("drm/msm/dsi: add support for 7nm DSI PHY/PLL")
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
> 
> I didn't fully test this, but according to msm-4.14, msm-4.19 and
> display drivers techpack this change is required on all 7nm- PHYs
> (including the SM8150).

Thanks.

This was suggested to me in non-public talks so let's add original
credits as well:

Reported-by: Abhinav Kumar <quic_abhinavk@...cinc.com>

Best regards,
Krzysztof