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Message-Id: <174063096232.3733075.4572201293177555361.b4-ty@linaro.org>
Date: Thu, 27 Feb 2025 06:37:28 +0200
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Rob Clark <robdclark@...il.com>,
Abhinav Kumar <quic_abhinavk@...cinc.com>,
Sean Paul <sean@...rly.run>,
Marijn Suijten <marijn.suijten@...ainline.org>,
David Airlie <airlied@...il.com>,
Simona Vetter <simona@...ll.ch>,
linux-arm-msm@...r.kernel.org,
dri-devel@...ts.freedesktop.org,
freedreno@...ts.freedesktop.org,
linux-kernel@...r.kernel.org,
Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Subject: Re: [PATCH RFC] drm/msm/dsi/phy: Program clock inverters in correct register
On Wed, 29 Jan 2025 12:55:04 +0100, Krzysztof Kozlowski wrote:
> Since SM8250 all downstream sources program clock inverters in
> PLL_CLOCK_INVERTERS_1 register and leave the PLL_CLOCK_INVERTERS as
> reset value (0x0). The most recent Hardware Programming Guide for 3 nm,
> 4 nm, 5 nm and 7 nm PHYs also mention PLL_CLOCK_INVERTERS_1.
>
>
Applied, thanks!
[1/1] drm/msm/dsi/phy: Program clock inverters in correct register
https://gitlab.freedesktop.org/lumag/msm/-/commit/baf490728777
Best regards,
--
Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
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