linux-kernel - Re: Config space access to Mediatek MT7922 doesn't work after device reset in Xen PV dom0 (regression, Linux 6.12)

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Message-ID: <Z5yLnDGeu7SVSLUU@mail-itl>
Date: Fri, 31 Jan 2025 09:36:43 +0100
From: Marek Marczykowski-Górecki <marmarek@...isiblethingslab.com>
To: Jan Beulich <jbeulich@...e.com>
Cc: Bjorn Helgaas <helgaas@...nel.org>, Bjorn Helgaas <bhelgaas@...gle.com>,
	Jürgen Groß <jgross@...e.com>,
	Roger Pau Monné <roger.pau@...rix.com>,
	Boris Ostrovsky <boris.ostrovsky@...cle.com>,
	xen-devel <xen-devel@...ts.xenproject.org>,
	linux-kernel@...r.kernel.org, regressions@...ts.linux.dev,
	Felix Fietkau <nbd@....name>, Lorenzo Bianconi <lorenzo@...nel.org>,
	Ryder Lee <ryder.lee@...iatek.com>
Subject: Re: Config space access to Mediatek MT7922 doesn't work after device
 reset in Xen PV dom0 (regression, Linux 6.12)

On Fri, Jan 31, 2025 at 08:13:37AM +0100, Jan Beulich wrote:
> On 30.01.2025 22:31, Bjorn Helgaas wrote:
> > On Thu, Jan 30, 2025 at 10:30:33AM +0100, Jan Beulich wrote:
> >> On 30.01.2025 05:55, Marek Marczykowski-Górecki wrote:
> >>> (XEN) d0v1 conf read cf8 0x80010088 bytes 2 offset 2 data 0x9
> > 
> > PCIe Cap at 0x80, PCI_EXP_DEVCTL is 0x08, PCI_EXP_DEVSTA is 0x0a.
> > 
> > 0x80010088 would be PCI_EXP_DEVCTL (a 2-byte register), maybe offset 2
> > gets us to PCI_EXP_DEVSTA?  Not sure.
> > 
> >   0x0001 PCI_EXP_DEVSTA_CED /* Correctable Error Detected */
> >   0x0008 PCI_EXP_DEVSTA_URD /* Unsupported Request Detected */
> > 
> > Not impossible that these would be set.  Lots of URs happen during
> > enumeration and we're not very good about cleaning these up.
> > Correctable errors are common for some devices.  lspci -vv would
> > decode the PCIe cap registers, including this.
> > 
> >>> (XEN) d0v1 conf read cf8 0x80010088 bytes 2 offset 0 data 0x2910
> > 
> > PCI_EXP_DEVCTL:
> >   0x2000 PCI_EXP_DEVCTL_READRQ_512B
> >   0x0800 PCI_EXP_DEVCTL_NOSNOOP_EN
> >   0x0100 PCI_EXP_DEVCTL_EXT_TAG
> >   0x0010 PCI_EXP_DEVCTL_RELAX_EN
> > 
> >>> (XEN) d0v1 conf write cf8 0x80010088 bytes 2 offset 0 data 0xa910
> > 
> > PCI_EXP_DEVCTL:
> >   set 0x8000 PCI_EXP_DEVCTL_BCR_FLR
> > 
> > This looks like the actual FLR being initiated.
> > 
> >> This is the express capability's Link Control 2 Register afaict.
> > 
> > Unless I'm missing something this is actually Device Control.  So far
> > I think this all looks OK.  The next part:
> 
> What you say is very plausible as far as the observed behavior goes,
> but: According to the lspci output provided earlier the express
> capability is at 58 (hex). 

lspci in the log says:

	Capabilities: [80] Express Endpoint, IntMsgNum 0

I think you confused device config space with bridge config space.

> Hence here we're 30 (hex) into the
> capability, which according to the spec I'm looking at is Link
> Control 2. Yet as said - with what you say being plausible, likely
> I'm simply getting something very wrong.
> 
> Jan

-- 
Best Regards,
Marek Marczykowski-Górecki
Invisible Things Lab

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