linux-kernel - Re: [PATCH v5 3/5] arm64: dts: agilex: add dtsi for PCIe Root Port

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <41edda71-de9d-e4e0-ef62-83e98f753e@linux.intel.com>
Date: Sat, 1 Feb 2025 10:07:19 -0800 (PST)
From: matthew.gerlach@...ux.intel.com
To: Frank Li <Frank.li@....com>
cc: lpieralisi@...nel.org, kw@...ux.com, manivannan.sadhasivam@...aro.org, 
    robh@...nel.org, bhelgaas@...gle.com, krzk+dt@...nel.org, 
    conor+dt@...nel.org, dinguyen@...nel.org, joyce.ooi@...el.com, 
    linux-pci@...r.kernel.org, devicetree@...r.kernel.org, 
    linux-kernel@...r.kernel.org, matthew.gerlach@...era.com, 
    peter.colberg@...era.com
Subject: Re: [PATCH v5 3/5] arm64: dts: agilex: add dtsi for PCIe Root Port



On Wed, 29 Jan 2025, Frank Li wrote:

> On Mon, Jan 27, 2025 at 11:35:48AM -0600, Matthew Gerlach wrote:
>> Add the base device tree for support of the PCIe Root Port
>> for the Agilex family of chips.
>>
>> Signed-off-by: Matthew Gerlach <matthew.gerlach@...ux.intel.com>
>> ---
>> v3:
>>  - Remove accepted patches from patch set.
>>
>> v2:
>>  - Rename node to fix schema check error.
>> ---
>>  .../intel/socfpga_agilex_pcie_root_port.dtsi  | 55 +++++++++++++++++++
>>  1 file changed, 55 insertions(+)
>>  create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi
>> new file mode 100644
>> index 000000000000..50f131f5791b
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi
>> @@ -0,0 +1,55 @@
>> +// SPDX-License-Identifier:     GPL-2.0
>> +/*
>> + * Copyright (C) 2024, Intel Corporation
>> + */
>> +&soc0 {
>> +	aglx_hps_bridges: fpga-bus@...00000 {
>> +		compatible = "simple-bus";
>> +		reg = <0x80000000 0x20200000>,
>> +		      <0xf9000000 0x00100000>;
>> +		reg-names = "axi_h2f", "axi_h2f_lw";
>> +		#address-cells = <0x2>;
>> +		#size-cells = <0x1>;
>> +		ranges = <0x00000000 0x00000000 0x80000000 0x00040000>,
>> +			 <0x00000000 0x10000000 0x90100000 0x0ff00000>,
>> +			 <0x00000000 0x20000000 0xa0000000 0x00200000>,
>> +			 <0x00000001 0x00010000 0xf9010000 0x00008000>,
>> +			 <0x00000001 0x00018000 0xf9018000 0x00000080>,
>> +			 <0x00000001 0x00018080 0xf9018080 0x00000010>;
>> +
>> +		pcie_0_pcie_aglx: pcie@...000000 {
>> +			reg = <0x00000000 0x10000000 0x10000000>,
>> +			      <0x00000001 0x00010000 0x00008000>,
>> +			      <0x00000000 0x20000000 0x00200000>;
>> +			reg-names = "Txs", "Cra", "Hip";
>> +			interrupt-parent = <&intc>;
>> +			interrupts = <GIC_SPI 0x14 IRQ_TYPE_LEVEL_HIGH>;
>> +			interrupt-controller;
>> +			#interrupt-cells = <0x1>;
>> +			device_type = "pci";
>> +			bus-range = <0x0000000 0x000000ff>;
>> +			ranges = <0x82000000 0x00000000 0x00100000 0x00000000 0x10000000 0x00000000 0x0ff00000>;
>
> This convert to pci address 0x0010_0000..0x1000_0000 from parent bus address
> 0x1000_0000..0x1ff0_0000
>
> aglx_hps_bridges bridge convert 0x90100000..0xa000_0000 (cpu address) to
> 0x1000_0000..0x1ff0_0000 according to ranges[1](second entry).
>
> Just want to confirm that "0x1000_0000..0x1ff0_0000" is actually reflect
> hardware behavior.

As far as I know, these conversions reflect the actual hardware behavior, 
but I will investigate further to confirm.

>
> On going a thread
> https://lore.kernel.org/linux-pci/Z5pfiJyXB3NtGSfe@lizhi-Precision-Tower-5810/T/#t
>
> Try to clean up all cpu_addr_fixup() or similar fixup() in pci root complex
> drivers, but which require dtsi reflect the real hardware behavior.
>
> In most current pci driver, even "0x1000_0000..0x1ff0_0000" is wrong, it
> still work by drivers' fixup. If dts correct descript hardware, these
> fixup can be removed.

The current driver, drivers/pci/controller/pcie-altera.c, does not have 
any cpu_addr_fix(); so I think the dts is properly describing the 
hardware, but I will continue to investigate and follow the thread
to clean the fixups.

>
> best regards
> Frank

Thanks for the feedback,
Matthew Gerlach

>
>> +			msi-parent = <&pcie_0_msi_irq>;
>> +			#address-cells = <0x3>;
>> +			#size-cells = <0x2>;
>> +			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
>> +			interrupt-map = <0x0 0x0 0x0 0x1 &pcie_0_pcie_aglx 0 0 0 0x1>,
>> +					<0x0 0x0 0x0 0x2 &pcie_0_pcie_aglx 0 0 0 0x2>,
>> +					<0x0 0x0 0x0 0x3 &pcie_0_pcie_aglx 0 0 0 0x3>,
>> +					<0x0 0x0 0x0 0x4 &pcie_0_pcie_aglx 0 0 0 0x4>;
>> +			status = "disabled";
>> +		};
>> +
>> +		pcie_0_msi_irq: msi@...08080 {
>> +			compatible = "altr,msi-1.0";
>> +			reg = <0x00000001 0x00018080 0x00000010>,
>> +			      <0x00000001 0x00018000 0x00000080>;
>> +			reg-names = "csr", "vector_slave";
>> +			interrupt-parent = <&intc>;
>> +			interrupts = <GIC_SPI 0x13 IRQ_TYPE_LEVEL_HIGH>;
>> +			msi-controller;
>> +			num-vectors = <0x20>;
>> +			status = "disabled";
>> +		};
>> +	};
>> +};
>> --
>> 2.34.1
>>
>