linux-kernel - Re: [PATCH v2 1/3] mtd: rawnand: cadence: support deferred prob when DMA is not ready

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Message-ID: <877c6357o5.fsf@bootlin.com>
Date: Thu, 06 Feb 2025 18:01:30 +0100
From: Miquel Raynal <miquel.raynal@...tlin.com>
To: "Rabara, Niravkumar L" <niravkumar.l.rabara@...el.com>
Cc: Richard Weinberger <richard@....at>,  Vignesh Raghavendra
 <vigneshr@...com>,  "linux@...blig.org" <linux@...blig.org>,  Shen Lichuan
 <shenlichuan@...o.com>,  Jinjie Ruan <ruanjinjie@...wei.com>,
  "u.kleine-koenig@...libre.com" <u.kleine-koenig@...libre.com>,
  "linux-mtd@...ts.infradead.org" <linux-mtd@...ts.infradead.org>,
  "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
  "stable@...r.kernel.org" <stable@...r.kernel.org>
Subject: Re: [PATCH v2 1/3] mtd: rawnand: cadence: support deferred prob
 when DMA is not ready

Hello,

>> >> > My apologies for the confusion.
>> >> > Slave DMA terminology used in cadence nand controller bindings and
>> >> > driver is indeed confusing.
>> >> >
>> >> > To answer your question it is,
>> >> > 1 - External DMA (Generic DMA controller).
>> >> >
>> >> > Nand controller IP do not have embedded DMA controller (2 -
>> >> > peripheral
>> >> DMA).
>> >> >
>> >> > FYR, how external DMA is used.
>> >> > https://elixir.bootlin.com/linux/v6.13.1/source/drivers/mtd/nand/ra
>> >> > w/c
>> >> > adence-nand-controller.c#L1962
>> >>
>> >> In this case we should have a dmas property (and perhaps dma-names), no?
>> >>
>> > No, I believe.
>> > Cadence NAND controller IP do not have dedicated handshake interface
>> > to connect with DMA controller.
>> > My understanding is dmas (and dma-names) are only used for the
>> > dedicated handshake interface between peripheral and the DMA controller.
>> 
>> I don't see well how you can defer if there is no resource to grab. And if there is
>> a resource to grab, why is it not described anywhere?
>> 
>
> Since NAND controller do not have handshake interface with DMA controller.
> Driver is using external DMA for memory-to-memory copy.

I'm sorry you lost me again. What do you mean handshake? There is no
request line? There is no way the NAND controller can trigger DMA
transfers?

What do you mean mem-to-mem, how is this useful to the controller?

> Your point is since the driver is using external DMA and it should be
> described in bindings?

Yes. But maybe I still don't get it correctly.

Thanks,
Miquèl