linux-kernel - RE: [PATCH v2 1/3] mtd: rawnand: cadence: support deferred prob when DMA is not ready

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Message-ID: <BL3PR11MB653239DDBD9D8E7D413B60F4A2F42@BL3PR11MB6532.namprd11.prod.outlook.com>
Date: Tue, 4 Feb 2025 14:11:16 +0000
From: "Rabara, Niravkumar L" <niravkumar.l.rabara@...el.com>
To: Miquel Raynal <miquel.raynal@...tlin.com>
CC: Richard Weinberger <richard@....at>, Vignesh Raghavendra
	<vigneshr@...com>, "linux@...blig.org" <linux@...blig.org>, Shen Lichuan
	<shenlichuan@...o.com>, Jinjie Ruan <ruanjinjie@...wei.com>,
	"u.kleine-koenig@...libre.com" <u.kleine-koenig@...libre.com>,
	"linux-mtd@...ts.infradead.org" <linux-mtd@...ts.infradead.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"stable@...r.kernel.org" <stable@...r.kernel.org>
Subject: RE: [PATCH v2 1/3] mtd: rawnand: cadence: support deferred prob when
 DMA is not ready

Hi Miquel,

> -----Original Message-----
> From: Miquel Raynal <miquel.raynal@...tlin.com>
> Sent: Tuesday, 4 February, 2025 9:33 PM
> To: Rabara, Niravkumar L <niravkumar.l.rabara@...el.com>
> Cc: Richard Weinberger <richard@....at>; Vignesh Raghavendra
> <vigneshr@...com>; linux@...blig.org; Shen Lichuan <shenlichuan@...o.com>;
> Jinjie Ruan <ruanjinjie@...wei.com>; u.kleine-koenig@...libre.com; linux-
> mtd@...ts.infradead.org; linux-kernel@...r.kernel.org; stable@...r.kernel.org
> Subject: Re: [PATCH v2 1/3] mtd: rawnand: cadence: support deferred prob when
> DMA is not ready
> 
> On 04/02/2025 at 10:43:20 GMT, "Rabara, Niravkumar L"
> <niravkumar.l.rabara@...el.com> wrote:
> >> Hello,
> >>
> >> > My apologies for the confusion.
> >> > Slave DMA terminology used in cadence nand controller bindings and
> >> > driver is indeed confusing.
> >> >
> >> > To answer your question it is,
> >> > 1 - External DMA (Generic DMA controller).
> >> >
> >> > Nand controller IP do not have embedded DMA controller (2 -
> >> > peripheral
> >> DMA).
> >> >
> >> > FYR, how external DMA is used.
> >> > https://elixir.bootlin.com/linux/v6.13.1/source/drivers/mtd/nand/ra
> >> > w/c
> >> > adence-nand-controller.c#L1962
> >>
> >> In this case we should have a dmas property (and perhaps dma-names), no?
> >>
> > No, I believe.
> > Cadence NAND controller IP do not have dedicated handshake interface
> > to connect with DMA controller.
> > My understanding is dmas (and dma-names) are only used for the
> > dedicated handshake interface between peripheral and the DMA controller.
> 
> I don't see well how you can defer if there is no resource to grab. And if there is
> a resource to grab, why is it not described anywhere?
> 

Since NAND controller do not have handshake interface with DMA controller.
Driver is using external DMA for memory-to-memory copy. 

Your point is since the driver is using external DMA and it should be described in bindings? 

Thanks,
Nirav