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Message-ID: <CAAyq3SbnX8WgN9U=YbJ465q6SBWz6GMuykC4svd9jzjnC3EVFQ@mail.gmail.com>
Date: Mon, 10 Feb 2025 11:16:57 +0800
From: Cheng Ming Lin <linchengming884@...il.com>
To: Michael Walle <mwalle@...nel.org>
Cc: tudor.ambarus@...aro.org, pratyush@...nel.org, miquel.raynal@...tlin.com,
richard@....at, vigneshr@...com, linux-mtd@...ts.infradead.org,
linux-kernel@...r.kernel.org, alvinzhou@...c.com.tw, leoyu@...c.com.tw,
Cheng Ming Lin <chengminglin@...c.com.tw>
Subject: Re: [PATCH 1/2] mtd: spi-nor: macronix: Add post_sfdp fixups for Quad
Input Page Program
Hi Michael,
Michael Walle <mwalle@...nel.org> 於 2025年2月7日 週五 下午4:36寫道:
>
> Hi Cheng,
>
> > Although certain Macronix NOR flash support the Quad Input Page Program
> > feature, the corresponding information in the 4-byte Address
> > Instruction
> > Table of these flash is not properly filled. As a result, this feature
> > cannot be enabled as expected.
> >
> > To address this issue, a post_sfdp fixups implementation is required to
> > correct the missing information.
> >
> > Signed-off-by: Cheng Ming Lin <chengminglin@...c.com.tw>
> > ---
> > drivers/mtd/spi-nor/macronix.c | 23 +++++++++++++++++++++++
> > 1 file changed, 23 insertions(+)
> >
> > diff --git a/drivers/mtd/spi-nor/macronix.c
> > b/drivers/mtd/spi-nor/macronix.c
> > index 830da21eea08..ada17999ccbb 100644
> > --- a/drivers/mtd/spi-nor/macronix.c
> > +++ b/drivers/mtd/spi-nor/macronix.c
> > @@ -45,8 +45,26 @@ mx25l25635_post_bfpt_fixups(struct spi_nor *nor,
> > return 0;
> > }
> >
> > +static int
> > +macronix_qpp4b_post_sfdp_fixups(struct spi_nor *nor)
> > +{
> > + /* PP_1_1_4_4B is supported but missing in 4BAIT. */
> > + struct spi_nor_flash_parameter *params = nor->params;
> > +
> > + params->hwcaps.mask |= SNOR_HWCAPS_PP_1_1_4;
> > + spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_1_1_4],
> > + SPINOR_OP_PP_1_1_4_4B, SNOR_PROTO_1_1_4);
> > +
> > + return 0;
> > +}
> > +
> > static const struct spi_nor_fixups mx25l25635_fixups = {
> > .post_bfpt = mx25l25635_post_bfpt_fixups,
> > + .post_sfdp = macronix_qpp4b_post_sfdp_fixups,
> > +};
> > +
> > +static const struct spi_nor_fixups macronix_qpp4b_fixups = {
> > + .post_sfdp = macronix_qpp4b_post_sfdp_fixups,
> > };
> >
> > static const struct flash_info macronix_nor_parts[] = {
> > @@ -102,11 +120,13 @@ static const struct flash_info
> > macronix_nor_parts[] = {
> > .size = SZ_64M,
> > .no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
> > .fixup_flags = SPI_NOR_4B_OPCODES,
> > + .fixups = ¯onix_qpp4b_fixups,
> > }, {
> > .id = SNOR_ID(0xc2, 0x20, 0x1b),
> > .name = "mx66l1g45g",
> > .size = SZ_128M,
> > .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
> > + .fixups = ¯onix_qpp4b_fixups,
> > }, {
> > .id = SNOR_ID(0xc2, 0x23, 0x14),
> > .name = "mx25v8035f",
> > @@ -154,18 +174,21 @@ static const struct flash_info
> > macronix_nor_parts[] = {
> > .size = SZ_64M,
> > .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
> > .fixup_flags = SPI_NOR_4B_OPCODES,
> > + .fixups = ¯onix_qpp4b_fixups,
> > }, {
> > .id = SNOR_ID(0xc2, 0x25, 0x3a),
> > .name = "mx66u51235f",
> > .size = SZ_64M,
> > .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
> > .fixup_flags = SPI_NOR_4B_OPCODES,
> > + .fixups = ¯onix_qpp4b_fixups,
> > }, {
> > .id = SNOR_ID(0xc2, 0x25, 0x3c),
> > .name = "mx66u2g45g",
> > .size = SZ_256M,
> > .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
> > .fixup_flags = SPI_NOR_4B_OPCODES,
> > + .fixups = ¯onix_qpp4b_fixups,
> > }, {
> > .id = SNOR_ID(0xc2, 0x26, 0x18),
> > .name = "mx25l12855e",
>
> Could you also please share the SFDP dumps of these flashes with us?
Certainly, I can share the SFDP dumps of these flashes with you.
I will send them over shortly.
>
> Thanks,
> -michael
Thanks,
Cheng Ming Lin
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